Julian D. Ho

Multicast performance in shared-memory ATM switches

Abstract Inefficient multicasting in shared-memory ATM switches restricts the output rate of cells and therefore reduces the overall performance. This paper proposes multicast schemes that simultaneously expand multiple multicast cells. When a multicast cell is only partially expanded the remaining residue is sent in later cycles (cell-splitting). This paper uses simulations to analyze the steady-state and transient performance of the proposed shared-memory multicast schemes. The proposed adjustments to multicast routing increase the output rate of cells, which dramatically reduces the cell loss rate and substantially reduces the multicast delays. The order of unicast expansion has a large effect on the performance. The returns in performance diminish on further increasing the number of multicast cells that can be expanded.

Modeling shared-memory ATM switches with fluid-flow models

Shared-memory switches are developing as the principal switch architecture in ATM networks. This has created demand for efficient and accurate methods of analysis. But the increase in memory sizes used in switches make existing forms of analysis too computationally intensive. Fluid flow models do not include the buffer content in their states and therefore the number of states is buffer independent. This paper critically reviews existing fluid-flow models for shared-memory switches. The advantages of each model are used in developing a model that accurately and efficiently provides cell loss and delay values. The performance of the proposed model is compared with results obtained via simulation and other fluid-flow models. The number of states and the computational time of the fluid-flow models are significantly less than traditional discrete queuing models.

Modeling multicasting in shared-memory ATM switches

The importance of multicasting at the switch level is increasing with the number of applications that are demanding multicast services. We extend a fluid-flow model for unicast only shared-memory switches to include replicate-at-receive multicasting. The advantage of fluid-flow models is that they are buffer independent. This overcomes the state explosion problem experienced with Markov chain models when using large sized buffers. Our proposed model reduces the complexity of the switch so that the problem only requires the analysis of a single output queue. Under various input traffic conditions the performance of the model is compared against results obtained via simulation. With shorter computational time the proposed model produces results comparable to those from simulation.

A Markov chain model for replicate-at-send multicasting in shared-memory ATM switches

Replicate-at-send multicasting has the best performance of the multicasting schemes for shared-memory ATM switches. Specifically replicate-at-send-distinct address queue multicasting is the most adopted implementation because of its low hardware requirements. We present an analytical model for shared-memory switches with replicate-at-send-distinct address queue multicasting. Under various input traffic conditions the analytical model is shown to be accurate when compared to simulation results. We demonstrate that the model is accurate for a range of loads, with different ratios of multicast traffic and for a range of fanout sizes.

Performance of a large multicast ATM switch

In this paper, we present the design of a large self-routing multicast ATM switch. The switch consists of a sorting network followed by a 3-stage routing network. We first present a simple design of a large sorting network built using small sized shared memory that can be used as a building block for a large sorting network. Small sized shared memory is also used in the 3-stage routing network making the switch modular and easy to implement using current VLSI technology. As the network uses shared memory modules, multicasting functionality is easily built into the network. The performance of the proposed network is compared with an equivalent completely shared memory switch using computer simulations under bursty traffic model. The results show that the proposed network has better performance in terms of cell loss ratio than the completely shared memory switch under moderate to heavy traffic load (0.6 ≤ effective offered load ≤ 1.2). Furthermore, multicast cell delays are drastically improved.

Analytical models for replicate-at-send multicasting in shared-memory switches

Shared-memory switches are still in commercial use and in the future will possibly be used in large-scale multistage architectures. The need to handle multicasting is also growing. In this paper analytical models are presented for shared-memory switches with the Replicate-At-Send-distinct address queue multicast scheme. Models for both Random (Bernoulli) and Bursty (Correlated) traffic sources are presented. The models are accurate for various loads, with different ratios of multicast traffic and a range of fanout sizes. They can be further extended to analyse more complex multicast schemes or multistage architectures.

A growable shared-memory based multicast ATM switch

This paper presents an ATM switch that fulfils the architectural and service requirements of large-scale ATM switches. The proposed network is based on a 3-stage Clos network, with shared-memory ATM switches at the input and output stages to provide optimal cell loss and delay performance. The modularity of the Clos architecture means that the network is inherently growable and has a high level of fault-tolerance. The network uses small sized shared-memory switches, so that the network can be scaled to large sizes without any technological constraints. The proposed network can support multicast traffic because of the multicasting functionality within shared-memory switches. Unlike other Clos based networks, this paper proposes a simple distributive routing algorithm for any sized network. Distributive multicasting allows multiple multicast cells to be routed simultaneously through the network. Various network configurations are simulated for their cell loss and cell delay performance. The resulting cell loss rate in the proposed network is well below that of the completely-shared ATM switch and the multicast cell delays are drastically improved.

Modular design of a large multicast ATM switch

In this paper, we present the design of a large self routing multicast ATM switch. The switch consists of a sorting network followed by a 3-stage routing network. We first present a simple design of a large sorting network, built using a small sized shared memory that can be used as a building block for a large sorting network. The small sized shared memory is also used in the 3-stage routing network making the switch modular and easy to implement using current VLSI technology. As the network uses shared memory modules, multicasting functionality is easily built into the network. The performance of the proposed network is compared with an equivalent completely shared memory switch using computer simulations under bursty traffic model. The results show that the proposed network has better performance in terms of cell loss rate than the completely shared memory switch under moderate to heavy traffic load (0.6/spl les/effective offered load/spl les/1.2). Furthermore, multicast cell delays are drastically improved.

Analytical modeling of multicast-pushout in shared-memory ATM switches

We present an analytical model for a multicast-pushout write policy. The pushout scheme maintains a high switch throughput by providing an optimum balance of unicast and multicast cells in the buffer. The scheme is adaptive to changes in multicast traffic such as changing fanout sizes and input rates. We demonstrate that the model is accurate for various loads, ratios of multicast traffic and fanout sizes.

Modeling of replicate-at-send multicasting in shared-memory ATM switches

The low cell loss rates required from ATM switches can be achieved with shared-memory based switches using large buffers. In this paper we present a fluid flow model for replicata-at-send distinct address queue multicasting in a shared-memory switch. Due to its buffer independence the model can calculate the performance of large buffered switches. The proposed model significantly reduces computational times and produces results that closely approximate simulation. In some cases the model can produce results which are difficult to obtain via simulation, without resorting to special techniques such as importance sampling.