Jun-Sik Hwang

Application of Au-Sn eutectic bonding in hermetic radio-frequency microelectromechanical system wafer level packaging

Development of packaging is one of the critical issues toward realizing commercialization of radio-frequency-microelectromechanical system (RF-MEMS) devices. The RF-MEMS package should be designed to have small size, hermetic protection, good RF performance, and high reliability. In addition, packaging should be conducted at sufficiently low temperature. In this paper, a low-temperature hermetic wafer level packaging scheme for the RF-MEMS devices is presented. For hermetic sealing, Au-Sn eutectic bonding technology at temperatures below 300°C is used. Au-Sn multilayer metallization with a square loop of 70 µm in width is performed. The electrical feed-through is achieved by the vertical through-hole via filling with electroplated Cu. The size of the MEMS package is 1 mm × 1 mm × 700 µm. The shear strength and hermeticity of the package satisfies the requirements of MIL-STD-883F. Any organic gases or contamination are not observed inside the package. The total insertion loss for the packaging is 0.075 dB at 2 GHz. Furthermore, the robustness of the package is demonstrated by observing no performance degradation and physical damage of the package after several reliability tests.

Application of Au-Sn eutectic bonding in hermetic RF MEMS wafer level packaging

Recently the strong demands in wireless communication requires expanding development for the application of RF MEMS (Radio Frequency micro electro mechanical systems) sensing devices such as micro-switches, tunable capacitors because it offers lower power consumption, lower losses, higher linearity and higher Q factors compared with conventional communications components. To accelerate commercialization of RF MEMS products, development for packaging technologies is one of the most critical issues should be solved beforehand. Packaging for RF MEMS is more challenging compared with conventional IC (integrated Circuit) Packaging technologies because it has both electrical and mechanical component, a low temperature, and hermetic wafer level packaging technology is needed for RF MEMS device. Au-Sn metallization system has been successfully utilize for flip chip bonding in many applications such as optoelectronic packaging and microwave device because of their high strength, good wetting behaviors, and resistance for thermal fatigue compared with conventional Pb/Sn solder system. Au-Sn eutectic bonding is considered to be a promising low temperature, wafer level bonding technology. In this paper, Au-Sn eutectic bonding for RF MEMS application is presented, a closed square loop was designed for the bonding structure, test vehicle was prepared for DOE (Design of experiment) process for the optimization of bonding parameters, and bonding temperature and applied load are found to be the most critical parameters for the bonding result, bonding can be done at a relative low temperature below 300/spl deg/C. For bonded samples, shear strength, warpage, insertion loss and hermetic tests etc. are performed for the evaluation of bonding quality, AES (Auger Electron Spectrum) and SEM (Scanning Electron Microscopy) was also made to investigate the microstructure of bonded interface, and reliability test such as thermal shock and high temperature, high humidity storage test was performed for the evaluation of bonding quality.

A low temperature, hermetic wafer level packaging method for RF MEMS switch

In this paper, a low temperature hermetic wafer level packaging (WLP) scheme for RF-MEMS devices such as micro-switches is presented. The real component with size 1mm/spl times/1mm is composed of two parts: cap substrate and device substrate, cap substrate has a via-in-cavity structure with cavity depth of 20/spl mu/m. High aspect ratio via hole is fabricated by inductive coupled plasma-reactive ion etching (ICP-RIE) and electroplated with Cu for electrical feed-through. Eutectic bonding is still the most commonly used packaging technology at present. For the purpose of hermetic sealing, Au-Sn multilayer metallization with a close square loop of 100/spl mu/m width have been sputtered onto cap wafer surface as soldering system. Deposition of cap wafer metallization should be finished in one high vacuum chamber process in order to prevent oxidation of Sn layer during producing process. And Ti-Ni-Au combination structure is deposited and patterned on device wafer in accordance with the sealing and interconnection areas in cap wafer. Bonding is performed in wafer level using eutectic bonder (TPS-2000A, BNP science) at a relative low temperature of 280/spl deg/C for heating in static N/sub 2/ ambience for a period of time. As-bonded wafers are then diced into pieces and subjected to a series of performance test for evaluation. Shear strength of two bonded interfaces are measured for sample cells by shear tester ROYCE 552 100K to evaluate mechanical property. RF characteristics insertion loss at 2GHz has measured by HP 8510C network analyzer probe station, a total packaging insertion loss less than 0.05DB could be achieved. For hermeticity test, specific test vehicles which have a large cavity of 0.5/spl times/0.5/spl times/0.05cm/sup 3/ are designed for helium leak test based on M1T-STD-883F since real device cavity has a tiny volume of only 600/spl times/600/spl times/30/spl mu/m/sup 3/, test vehicles indicate a maximum equivalent leak rate in air of 1.6/spl times/10/sup -8/ mbar.l/sec. Also residual gas analysis (RGA) test is performed for bonded device sample. Reliability tests like thermal shock and high temperature, high humidity storage test are also performed according to MIL-STD-883F. For samples before and after reliability tests, measurements also have been made for comparison to evaluate the quality and reliability of packaging structure.

6B-6 An Ultra Small SAW RF Filter using Wafer Level Packaging Technology

Since a multitude of surface acoustic wave (SAW) filters are the key components for wireless communications, they play an important role in todays mobile phone evolution. Increasing the levels of functional integration and size reduction are therefore the major driving forces in recent SAW radio frequency (RF) filter development. This paper presents a pioneering work for design and fabrication of ultra small SAW filter package. A novel wafer level packaging technology based on through-wafer interconnection and wafer-to-wafer bonding is designed to achieve highly miniaturized SAW RF filters. Based on this technology, SAW RF filters for mobile phone systems are developed in the worlds smallest size of 1.0 times 0.8 times 0.25 mm3. It is shown that our newly developed SAW RF filter offers equal frequency characteristics compared with the conventional chip-sized package. And the reliability test result of hermetically sealed SAW filter package will be presented to verify its application to mobile phones. As a result of these developments, wafer-level packaged SAW RF filters will offer considerable advantages over conventional chip-sized packages in many aspects of performance and production, including size, cost, and further integration

The microfluxgate magnetic sensor having closed magnetic path

This paper presents a microfluxgate magnetic sensor in printed circuit board (PCB). In order to observe the effect of the closed magnetic path, the magnetic cores of rectangular ring and two bars were each fabricated. Each fluxgate sensor consists of five PCB stack layers including one layer magnetic core and four layers of excitation and pickup coils. The center layer as a magnetic core is made of a Co-based amorphous magnetic ribbon with extremely high dc permeability of /spl sim/100,000. Four outer layers as excitation and pickup coils have a planar solenoid structure and are made of copper foil. In the case of the fluxgate sensor having the rectangular ring-shaped core, excellent linear response over the range of -100 to +100 /spl mu/T is obtained with 780-V/T sensitivity at an excitation sine wave of 3 V/sub P-P/ and 360 kHz. The chip size of the fabricated sensing element is 7.3/spl times/5.7 mm/sup 2/. The very low power consumption of /spl sim/8 mW was measured.

Bottom Electrode Structures of Pt/RuO2/Ru on Polycrystalline Silicon for Low Temperature (Ba,Sr)TiO3 Thin Film Deposition

Electrode structures of Pt/RuO2/Ru on polysilicon and (Ba,Sr)TiO3(BST) thin films on Pt/RuO2/Ru/poly-Si structures were prepared by metal-organic chemical vapor deposition (MOCVD). The barrier layers of RuO2/Ru deposited by MOCVD showed a stable interface and did not affect the surface morphology of the platinum bottom electrode even at a high annealing temperature of 800°C in oxygen ambient. Contacts in the annealed state up to 800°C exhibited linear current-voltage characteristics with a constant specific contact resistance of 5.0 ×10-5 Ωcm2. The excellent leakage current characteristics and dielectric properties of 50-nm-thick BST films were due to the stable and smooth morphologies of the bottom electrodes at BST deposition temperature.

A study on wafer level molding for realizing 3-D integration

3D-IC packaging using through silicon via technology has been extensively developed to meet small form factor and low power consumption demands for next generation devices. A wafer molding technology is required for 3D chip integration. Wafer molding is carried out in the chip-to-wafer process to ensure suitable levels of mechanical strength are reached. The key to wafer level mold processing is the reduction of warpage. This paper discusses the material developments and steps taken for process optimization in the wafer molding process to reduce warpage. A 2 chip stack arrangement was used for this investigation, with a 12 inch bottom wafer containing vias, and 9×9 mm top chip wafers. The evaluation was run systematically in three major phases. In the first phase, the levels of warpage experienced during the packaging processes were simulated. The evaluation of three different types of material (Epoxy, Silicone and Hybrid) was carried out in the second phase. The third and final phase involved the testing for warpage at room and high temperature conditions of the epoxy and hybrid based resins. The silicone based resin was also evaluated with varying amounts of filler and adhesion promoter. The modulus and coefficient of thermal expansion (CTE) were found to be extremely important, since lowering this property would result in low warpage levels, both at room and high temperatures, which control the water absorption and temperature cycle reliability in the silicone based resin were established.

Slow scanning electromagnetic scanner for laser display

A small sized, low power consuming, shock proven optical scanner with a capacitive comb-type rotational sensor for the application of mobile projection display is designed, fabricated, and characterized. To get a 2-D video image, the present device horizontally scans a vertical line image made through a line-type diffractive spatial optical modulator. To minimize, device size as well as power consumption, the mirror surface is placed on the opposite side of the coil actuator. To prevent thermal deformation of the mirror, the mirror is partially connected to the center point of the coil actuator. To be shock proof, mechanical stoppers are constructed in the device. The scanner is fabricated from two silicon wafers and one glass wafer using bulk micromachining technology. The packaged scanner consists of the scanner chip, a pair of magnets, yoke rim, and base plate. The fabricated package size is 9.2×10×3 mm (0.28 cc) and the mirror size is 3×1.5 mm. The scanner chip receives no damage under the shock test with an impact of 2000 G in 1 ms. In the case of a full optical scan angle of 30 deg at 120-Hz driving frequency, linearity, repeatability, and power consumption are measured at 98%, 0.013 deg, and 60 mW, respectively, which are suitable for mobile display applications.

Contact Properties of Pt / RuO2 / Ru Electrode Structure Integrated on Polycrystalline Silicon

The buffer layers of RuO 2 /Ru in Pt/RuO 2 /Ru/poly-Si (polycrystalline silicon) structure were prepared by metallorganic chemical vapor deposition (MOCVD) and dc magnetron sputtering. The harrier layers of RuO 2 /Ru deposited by MOCVD showed a stable interface, and did not affect the surface morphology of the platinum bottom electrode even at a high annealing temperature of 800°C. The barrier layers effectively prevented the interdiffusion of Pt, O, and Si at annealing temperatures above 700°C in O 2 ambient. On the other hand, the barrier layers of RuO 2 /Ru formed by dc sputtering showed severe intermixing and strongly influenced the platinum morphology at high temperature annealing. Contacts in Pt/MOCVD(RuO 2 /Ru)/poly-Si and Pt/dc sputtered (RuO 2 /Ru)/poly-Si structures showed the specific contact resistance of 5.0 x 10 - 5 and 2.0 x 10 -3 Ω cm 2 , respectively. The barrier layers of RuO 2 /Ru formed by MOCVD in Pt/RuO 2 /Ru/poly-Si structure were attractive for integration of high dielectric constant (Ba,Sr)TiO 3 .

Microstructure of AuSn Wafer Bonding for RF-MEMS Packaging

RF-MEMS is one of the most potential applications for MEMS products. Eutectic solder wafer bonding is one of the attractive methods for RF-MEMS wafer level packaging. A process of gold-tin hermetical wafer bonding was developed in SAIT, Korean. Different UBM systems and thin films of gold-tin were deposited on cap wafer, RF-MEMS device wafer and substrate wafer (if needed). The bonding was performed in N2 ambience with pressure. The cross section of bonding layer had been studied using SEM/EDAX. The thickness of bonding layer is uniform, ranging from 5mum to 7mum. Pretreatment is important to obtain good adhesion and successful microstructure. Voids could be detected without ashing. Optimal process, such as plasma cleaning, would eliminate these voids. There existed different regions in the bonding layer due to inter-diffusion between Au-Sn and other elements. Different intermetallic formed at the bonding layer. The compositions of the intermetallic was identified by EDAX and analyzed according to the Au-Sn phase diagram. The microstructures of the bonding layer are similar for different bonding temperatures in experiments, which indicates lower bonding temperature can get the same hermetical sealing. Typically, there are Au rich layer, AuSn IMC layer and Sn/Au-Ni-Ti layer in the bonding layer between cap wafer and substrate wafer, while there are Au layer, Au-Sn-Ni compound layer in the bonding layer between device wafer and substrate wafer. From the EDAX analysis, different intermetallic compound (IMC) can be identified as AuSn2, AuSn and other composition. Hermetical and shear strength test were performed for as-bonded dice. The test results indicated there is little difference among different bonding process. Fracture surfaces after shear test were investigated as well. The fracture was inside Au-Sn IMC. It indicates the UBM selected is suitable for application. Reliability test was also performed