Jun-Young Jeon
Samsung
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Publication
Featured researches published by Jun-Young Jeon.
IEEE Journal of Solid-state Circuits | 1999
Hongil Yoon; Gi-Won Cha; Changsik Yoo; Nam-jong Kim; Keum-Yong Kim; Chang Ho Lee; Kyu-Nam Lim; Kyu-Chan Lee; Jun-Young Jeon; Tae Sung Jung; Hong-Sik Jeong; Tae-Young Chung; Kinam Kim; Soo In Cho
A double data rate (DDR) at 333 Mb/s/pin is achieved for a 2.5-V, 1-Gb synchronous DRAM in a 0.14-/spl mu/m CMOS process. The large density of integration and severe device fluctuation present challenges in dealing with the on-chip skews, packaging, and processing technology. Circuit techniques and schemes of outer DQ and inner control (ODIC) chip with a non-ODIC package, cycle-time-adaptive wave pipelining, and variable-stage analog delay-locked loop with the three-input phase detector can provide precise skew controls and increased tolerance to processing variations. DDR as a viable high-speed and low-voltage DRAM I/O interface is demonstrated.
Archive | 1994
Jun-Young Jeon
Archive | 1994
Jun-Young Jeon
Archive | 1995
Jun-Young Jeon
Archive | 1998
Jong-Hyun Choi; Jun-Young Jeon
Archive | 1996
Jun-Young Jeon
Archive | 1991
Jun-Young Jeon
Archive | 1991
Jun-Young Jeon; Dae-Je Jin
Archive | 1999
Hoon Ryu; Moon-chan Hwang; Jun-Young Jeon
Archive | 1996
Jun-Young Jeon; Gi-Won Cha; Sang-Jae Lee