Changsik Yoo

A 4.39–5.26 GHz LC-Tank CMOS Voltage-Controlled Oscillator With Small VCO-Gain Variation

A wide band CMOS LC-tank voltage controlled oscillator (VCO) with small VCO gain (KVCO) variation was developed. For small KVCO variation, serial capacitor bank was added to the LC-tank with parallel capacitor array. Implemented in a 0.18 mum CMOS RF technology, the proposed VCO can be tuned from 4.39 GHz to 5.26 GHz with the VCO gain variation less than 9.56%. While consuming 3.5 mA from a 1.8 V supply, the VCO has -113.65 dBc/Hz phase noise at 1 MHz offset from the carrier.

Active Power Factor Correction (PFC) Circuit With Resistor-Free Zero-Current Detection

An active power-factor correction (PFC) circuit is presented that employs a newly proposed resistor-free zero-current detection (ZCD). While the conventional ZCD requires either a sensing resistor or auxiliary transformer, the proposed ZCD requires only one OFF-chip capacitor. The active PFC circuit with the proposed resistor-free ZCD has been implemented in a 0.35-μm BCDMOS process and the power factor is improved up to 9% from the one employing the conventional ZCD. The proposed resistor-free ZCD scheme can be applied to any type of switch-mode dc-dc power converter.

A /spl plusmn/1.5-V, 4-MHz CMOS continuous-time filter with a single-integrator based tuning

A 4-MHz, fifth-order elliptic low-pass Gm-C filter is described whose characteristics are tuned by an on-chip automatic tuning circuit. The tuning circuit uses only one integrator as the master of tuning instead of problematic voltage controlled oscillator (VCO) and voltage controlled filter (VCF). MOS transistors in linear operation region perform the voltage-to-current conversion in an operational transconductance amplifier, and thereby we achieved /spl plusmn/1.5 V operation. A prototype filter was implemented in a 0.8-/spl mu/m double-poly, double-metal CMOS process. The filter exhibits the dynamic range of 57.6 dB and dissipates 10 mW with /spl plusmn/1.5-V supply. The stopband attenuation is better than 45.0 dB and the passband ripple is smaller than 1.0 dB.

A 1.8 V 700 Mb/s/pin 512 Mb DDR-II SDRAM with on-die termination and off-chip driver calibration

A 1.8 V 700 Mb/s/pin 512 Mb DDR-II SDRAM is JEDEC standard compliant. With the hierarchical I/O line and local sensing, t/sub AA/ /t/sub RCD//t/sub RP/ of 3/3/3 at 533 Mb/s are achieved in the design. For signal integrity at 533 Mb/s, off-chip driver calibration and on-die termination are employed.

Current Reusing VCO and Divide-by-Two Frequency Divider for Quadrature LO Generation

For low-power and accurate quadrature local oscillator (LO) signal generation, an LC-tank voltage controlled oscillator (VCO) operating at double the required LO-frequency reuses the bias current of divide-by-two frequency divider. The current reusing VCO and divide-by-two frequency divider are targeted to generate the LO signals for a 1.57 GHz global positioning system receiver. Implemented in a 0.18 mum CMOS technology, the current reusing VCO and divide-by-two frequency divider consumes 1.7mA from a 1.8 V supply. The measured phase noise is -120dBc/Hz at 1 MHz offset when the carrier frequency is 1.57GHz.

5-GHz Low-Phase Noise CMOS Quadrature VCO

A 5-GHz low-phase noise CMOS quadrature voltage controlled oscillator (QVCO) is described. Two differential pairs (one for negative gm generation and the other one for the coupling input) of each resonator have separate biasing transistors which are switched on and off by the coupling input of each resonator. The proposed QVCO implemented in a 0.13-mum CMOS technology shows 17-dB phase noise improvement from a conventional QVCO with constant tail current sources while the two QVCOs consume the same power of 5.28mW. The phase noise of the proposed QVCO is measured to be -102dBc/Hz and -117dBc/Hz at 100KHz and 1-MHz offset, respectively

A CMOS buffer without short-circuit power consumption

A new CMOS buffer without short-circuit power consumption is proposed. The gate-driving signal of the output pull-up (pull-down) transistor is fed back to the output pull-down (pull-up) transistor to get tri-state output momentarily, eliminating the short-circuit power consumption, The HSPICE simulation results verified the operation of the proposed buffer and showed the power-delay product is about 15% smaller than conventional tapered CMOS buffer.

A 2x2 MIMO Tri-Band Dual-Mode Direct-Conversion CMOS Transceiver for Worldwide WiMAX/WLAN Applications

This paper describes a fully integrated 130 nm CMOS 2×2 MIMO tri-band dual-mode transceiver for fixed and mobile WiMAX and IEEE 802.11a/b/g/n applications. The proposed transceiver features reduced RF interface (only 4 RF pins) with the wideband circuit topology of the LNA and drive amplifier that minimizes the performance degradation. With carefully chosen LO frequency planning, the transceiver is capable of operating at 2.3-2.7 GHz, 3.3-3.9 GHz, and as well as 5.1-5.9 GHz bands covering whole frequency spectrum of fixed and mobile WiMAX and WLAN. The measured noise figure of the receiver is 3.6-4.2, 4.2-4.7, and 5.4-6.2 dB for each 2/3/5 GHz bands respectively. The measured PLL phase noise from 1 kHz to 10 MHz is 0.5/0.8/0.95 rms degree for 2/3/5 GHz bands respectively. The transceiver ensures low EVM over the wide dynamic range due to linear RX and TX signal paths and low integrated PLL phase noise characteristics.

A CCM/DCM Dual-Mode Synchronous Rectification Controller for a High-Efficiency Flyback Converter

A dual-mode synchronous rectification (SR) controller supporting both the continuous-conduction mode and discontinuous-conduction mode is developed to improve the power efficiency of a flyback converter. The dual-mode SR controller ensures nonoverlapped turning-on of the primary and secondary switches by monitoring the voltage level of the secondary switch. The dual-mode SR controller requiring four pins and only one external resistor has been implemented in a 0.35-μm BCDMOS process and applied to a 50-W flyback converter. The efficiency of the flyback converter is improved by upto 6.8% when the dual-mode SR controller is employed compared to the one employing the conventional SR controller.

A Two-Phase Interleaved Power Factor Correction Boost Converter With a Variation-Tolerant Phase Shifting Technique

This paper presents a two-phase interleaved critical conduction mode (CRM) power factor correction boost converter with a variation-tolerant phase shifter (VTPS), which ensures accurate 180° phase shift between the two interleaved converters. A feedback loop similar to a phase-locked loop controls the amount of the phase shifting of the VTPS. The proposed VTPS has better immunity of process, supply, and temperature variations than the conventional phase shifter. A 320-W two-phase interleaved CRM boost converter prototype has been implemented, while the proposed VTPS and conventional interleaving phase shifter can be selectively applied to compare the performance of the proposed technique with the conventional one. Experimental results show that the two-phase interleaved CRM boost converter has better performance with the proposed VTPS. The proposed VTPS circuit can be applied to any type of interleaved switching power converter.