June Moon

High performance PRAM cell scalable to sub-20nm technology with below 4F2 cell size, extendable to DRAM applications

A PRAM cell with great scalability and high speed operation capability with excellent reliability below 20nm technology was demonstrated. This has the meaning of the potential applicable to the technology area of scaling limitation of DRAM cell. We fabricated a confined PRAM cell with 7.5nm×17nm of below 4F2. In particular, Sb-rich Ge-Sb-Te phase change material was employed for high speed operation below 30nsec. The excellent writing endurance performance was predicted to maintain up to 6.5E15cycles by reset program energy acceleration. Its data retention was 4.5 years at 85°C which is enough for DRAM application.

A unified 7.5nm dash-type confined cell for high performance PRAM device

We present a new-type confine structure within 7.5 nm width dash-contact for sub 20 nm generation PRAMs. Phase change material (PCM) by chemical vapor deposition (CVD) was perfectly filled in a 7.5 nm width dash-contact without void along with 30 nm depth. By adopting confined CVD-PCM, we were able to reduce the reset current below ~160 muA and to obtain high reliability. In addition, the programming time of dash-confined cell was much improved to 50 ns due to volume confinement of PCM cell. Consequently, we firstly demonstrate the high performance of the 7.5 nm width confined cell, which is the smallest size close to physical limit.

MRAM with novel shaped cell using synthetic anti-ferromagnetic free layer

Magnetic random access memory (MRAM) with magnetic tunnel junction (MTJ) using synthetic anti-ferromagnetic (SAF) free layers of various shapes has been developed. SAF free layers show the predominance in the scalability compared with a conventional single free layer. It is also revealed that a novel shaped MTJ with a SAF free layer has a remarkably large writing margin.

On the gate oxide scaling of high performance CMOS transistors

The gate oxide scalability of high performance CMOS transistor has been investigated. In terms of gate leakage, the T/sub ox/ can be scaled down to at least 8 /spl Aring/ with I/sub G/ not exceeding I/sub off/ limit suggested by ITRS. To reduce boron penetration, remote-plasma-nitridation (RPN) oxides were studied. Devices with RPN oxides showed excellent resistance against boron penetration, improved hole mobility, reduced gate leakage, and improved transistor performance. The gate oxide scalability can be extended using the RPN process.

Interface states as an active component for 20 nm gate-length planar MOSFET with electrostatic channel extension (ESCE)

Electrostatic channel extension (ESCE) MOSFET, a transistor with static inversion layer formed by interface fixed charge is fabricated in planar bulk structure down to 20 nm gate-length. The 24 nm gate-length ESCE transistor with current 80 nm gate-length SRAM technology shows the excellent drive currents of 1.0 mA/mum with IOFF of 93 nA/mum at VDS = 1 V. Moreover, the ESCE transistor with the gate oxide thickness of 10 Aring shows effectively suppressed gate-oxide leakage, very low GIDL, high breakdown voltage (> 6 V), immunity from CD variance, and robust reliability. The ESCE scheme is very promising to overcome the scale-down limit of planar transistor beyond 20 nm with ultra-low cost

The effects of TaN thickness and strained substrate on the performance and PBTI characteristics of poly-Si/TaN/HfSiON MOSFETs

The effects of TaN metal-gate thickness on the electrical characteristics of poly-Si/metal-gate/HfSiON MOSFETs have been investigated. Too thin TaN was reactive with poly-Si gate, which led to the formation of Si-doped metal gate. As a result, the work function of the metal gate was reduced and the capacitance increased while generating traps in HfSiON films. P-MOSFET using poly-Si/TaN gate with channel engineering in strained-Si substrate showed threshold voltage of - 0.45 V at W/L= 10/1 /spl mu/m and improved MOSFET characteristics.

Highly reliable 50nm-thick PZT capacitor and low voltage FRAM device using Ir/SrRuO/sub 3//MOCVD PZT capacitor technology

For the first time, we successfully developed highly reliable 50nm-thick polycrystalline PZT capacitor using noble Ir/SrRuO/sub 3/ top electrode and MOCVD PZT technology. In the 50nm-thick PZT capacitor, 33/spl mu/C/cm/sup 2/ of remanent polarization and 0.7V of saturation voltage have been demonstrated. Moreover, after 100hrs of bake-time at 150/spl deg/C, opposite-state polarization margin was over 23/spl mu/C/cm/sup 2/, which is world-wide best result so far achieved. Using this capacitor technology, highly reliable low voltage operating embedded FRAM device was successfully developed.

MRAM with lamellar structure as free layer

The key factors to improve the switching characteristics are systematically analyzed to develop high density MRAM with a reliable operating margin. We demonstrated that roughness control of MTJ films, choice of free layer materials with small Ms, and optimized cell shape can effectively suppress the switching distribution. As a novel free layer scheme, a lamellar structure is proposed and found to improve the switching characteristics by suppressing the grain growth in the ferromagnetic layer.

Investigation of hot carrier effects in n-MOSFETs thick oxide with HfSiON and SiON gate dielectrics

This paper reports the reliability characteristics of poly gated n-MOSFETs with HfSiON and SiON gate dielectrics in both thin and thick oxide of dual gate oxide scheme. Hot carrier stress (HCS) at Isub, max condition on thick oxide is found to be the most critical part among the various reliability concerns. Regardless of gate dielectric and gate oxide thickness, the degradation behavior of the condition of Isub, max and Vg=Vd HCS is mainly SS increase and Vth shift, respectively. Therefore, for precise evaluation of the device reliability, it is necessary that HC immunity at Isub, max stress should be checked in thick oxide transistor below 50 nm design rule era.

Noble High Density Probe Memory using Ferroelectric Media beyond Sub-10 nm Generation

Feasibility of high density probe-based memory with polycrystalline ferroelectric media has been demonstrated for next memory applications beyond sub-10 nm generation. Noble chemical-mechanical-polishing (CMP) method was employed to fabricate a very even surface on polycrystalline MOCVD Pb(Zr,Ti)O3 (PZT) media. On the CMP processed PZT media, domain dot array was able to be written and read even at grain boundary region by PFM technique. Moreover, 15 nm-sized domain dot was successfully demonstrated on 50 nm-thick PZT media. Also for the first time, we successfully demonstrated that the polycrystalline ultra thin 7 nm-thick PZT media has good ferroelectric properties