Jung-Chak Ahn

Micro villus patterning (MVP) technology for 256 Mb DRAM stack cell

Micro villus patterning (MVP) technology which delivers the maximized cell capacitance is discussed. The key feature of the MVP technology is the formation of a hemispherical grain (HSG) archipelago and its transference to the underlayered oxide. The HSG archipelago pattern is produced on the oxide layer, and, by using that pattern as an etch mask, the oxide archipelago pattern is again transferred to the storage poly for the formation of villus bars by anisotropic dry etch. After the etching process, the oxide etch mask pattern is stripped away by using oxide wet etchant, so that additional Fin undercut structure is achieved underneath the main body. The main body of the storage electrode can be formed by single deposition and etch process, so that the storage electrode structure is strong enough to maintain its physical stability in spite of the complication of its shape. A 256-Mb DRAM-cell size of 0.6 approximately 0.8 mu m/sup 2/ having more than 30 fF of cell capacitance with a stack structure, has been realized.<<ETX>>

Bulk planar 20nm high-k/metal gate CMOS technology platform for low power and high performance applications

A 20 nm logic device technology for low power and high performance application is presented with the smallest contacted-poly pitch (CPP) of minimal 80 nm ever reported in bulk Si planar device. We have achieved nFET and pFET drive currents of 770 µA/µm and 756 µA/µm respectively at 0.9 V and 1 nA/µm Ioff with the novel high-k/metal (HKMG) gate stack and advanced strain engineering. Short channel effect is successfully suppressed thanks to the optimized shallow junction, resulting in excellent DIBL and subthreshold swing below 120 mV and 90 mV/dec, respectively. In addition, full functionality of SRAM device with 20 nm technology architecture is confirmed.

50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications

A 90 nm generation logic technology with Cu/low-k interconnects is reported. 50 nm transistors are employed using gate oxide 1.3 nm in thickness and operating at 1.0 V. High speed transistors have drive currents of 870 /spl mu/A/pm and 360 /spl mu/A//spl mu/m for NMOS and PMOS respectively, while generic transistors have currents of 640 /spl mu/A//spl mu/m and 260 /spl mu/A//spl mu/m respectively. Low power process using high-k gate dielectrics and SOI process are also provided in this technology. The low-k SiOC material with 2.9 in the k value is used for 9 layers of dual damascene Cu/low-k interconnects. The effective k (k/sub eff/) value of interconnect is about 3.6. Fully working 6-T SRAM cell with an area of 1.1 /spl mu/m/sup 2/ and SNM value of 330 mV is obtained. For MIM capacitor, voltage coefficient of capacitance is less than 20 ppm/V.

7.1 A 1/4-inch 8Mpixel CMOS image sensor with 3D backside-illuminated 1.12μm pixel with front-side deep-trench isolation and vertical transfer gate

According to the trend towards high-resolution CMOS image sensors, pixel sizes are continuously shrinking, towards and below 1.0μm, and sizes are now reaching a technological limit to meet required SNR performance [1-2]. SNR at low-light conditions, which is a key performance metric, is determined by the sensitivity and crosstalk in pixels. To improve sensitivity, pixel technology has migrated from frontside illumination (FSI) to backside illumiation (BSI) as pixel size shrinks down. In BSI technology, it is very difficult to further increase the sensitivity in a pixel of near-1.0μm size because there are no structural obstacles for incident light from micro-lens to photodiode. Therefore the only way to improve low-light SNR is to reduce crosstalk, which makes the non-diagonal elements of the color-correction matrix (CCM) close to zero and thus reduces color noise [3]. The best way to improve crosstalk is to introduce a complete physical isolation between neighboring pixels, e.g., using deep-trench isolation (DTI). So far, a few attempts using DTI have been made to suppress silicon crosstalk. A backside DTI in as small as 1.12μm-pixel, which is formed in the BSI process, is reported in [4], but it is just an intermediate step in the DTI-related technology because it cannot completely prevent silicon crosstalk, especially for long wavelengths of light. On the other hand, front-side DTIs for FSI pixels [5] and BSI pixels [6] are reported. In [5], however, DTI is present not only along the periphery of each pixel, but also invades into the pixel so that it is inefficient in terms of gathering incident light and providing sufficient amount of photodiode area. In [6], the pixel size is as large as 2.0μm and it is hard to scale down with this technology for near 1.0μm pitch because DTI width imposes a critical limit on the sufficient amount of photodiode area for full-well capacity. Thus, a new technological advance is necessary to realize the ideal front DTI in a small size pixel near 1.0μm.

A 1/2.33-inch 14.6M 1.4μm-pixel backside-illuminated CMOS image sensor with floating diffusion boosting

As pixel sizes continue to scale down, backside-illuminated (BSI) technology has been recently adopted as a solution to improve pixel SNR performance [1,2]. In addition, as the application of image sensors widens from digital still cameras to digital camcorders, high-resolution and high-speed operation are required. This paper presents 1/2.33-inch 14.6Mpixel CMOS image sensor employing a 1.4μm BSI pixel architecture with a floating-diffusion (FD) boosting scheme that enables high SNR and high speed read-out.

F4: High-speed image sensor technologies

High speed imaging is one of the fastest growing semiconductor markets. Growth is currently driven by consumer and industrial applications such as HD video, slow motion play-back, machine vision, 3D range capture, and robotics. This forum will present chip architectures, circuits, and system-level solutions used in CCD and CMOS image sensors for high speed cameras. Technology topics include photon detection devices, pixel circuits and array readout circuits, A/D converters, image processing and interface circuits presented by world leading experts from industry and academia. The potential applications of this technology will be demonstrated by ultra high speed capture solutions for 3D range imaging and robotics. For advanced applications, techniques for outputing high-throughput pixel data using analog or digital interfaces are described. The forum will conclude with a panel discussion where the attendees have the opportunity to ask questions and to share their views, and this all-day forum encourages open information exchange. The targeted participants are circuit designers and concept engineers working on image sensor and camera system design.

10nm 2 nd generation BEOL technology with optimized illumination and LELELELE

10nm 2nd generation BEOL technology is described with an optimized illumination system and multi-patterning lithography. While the optimized illumination system offered a possibility to pattern reduced metal pitches in the preferred orientation, difficulties of T-T and T-S patterning still remained. It was overcome by increasing the number of available multi-patterning colors from 2 to 4. First-ever implementation of LELELELE with tight inter-color misalignment control increased scalability up to 17.1% and was demonstrated with SRAM 128Mb yield.

Advanced image sensor technology for pixel scaling down toward 1.0µm (Invited)

As pixel size of image sensors shrinks down rapidly, we are reaching technical barrier to get the required low light performance. In this paper, recent advanced technologies such as backside illumination, new color filter array, low F-number with extended depth of field technologies, etc. are introduced to overcome such a barrier. It is shown that the integration of these advanced sensor technologies can make pixel size shrink down toward 1.0 mum with the required performance.

Robust process integration of 0.78 /spl mu/m/sup 2/ embedded SRAM with NiSi gate and low-K Cu interconnect for 90 nm SoC applications

The smallest high density embedded 0.78 /spl mu/m/sup 2/ 6T-SRAM cell for high performance 90 nm SoC applications was successively integrated by using leading edge technologies such as 193 nm ArF lithography, 1.2 nm gate oxide, 50 nm transistor and Cu dual damascene with low-K dielectric. Fully working for SRAM shows the SNM value above 200 mV. Device current of 870 /spl mu/A//spl mu/m and 390 /spl mu/A//spl mu/m for NMOS and PMOS respectively is achieved at 1.0 V operation. Reliability life time on hot carrier immunity shows more than 10 years.