Jung-Ping Yang

12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications

Mobile applications, such as smartphones streaming HD videos or virtual-reality headsets rendering 3D landscapes, need SRAM memories that can be put in a low-power state to extend battery life, but can also offer high performance operation when required [1]. This paper will merge a 10nm technology with a dual-rail SRAM architecture to achieve superior power savings and performance scaling in comparison to the previous 16nm technology node [2]. Due to its simple design and area efficient layout, the 6T SRAM bitcell continues to be the primary memory technology used in almost all SoC and processor designs in high volume manufacturing today. The 10nm technology uses low-leakage, high-performance, second-generation FinFET transistors; it also offers a 6T cell (0.042µm2), for area and power savings, that does not require read or write assist circuits to achieve low voltage (Vmin) operation. This bitcell uses a fin ratio of 1∶2∶2 (PU:PG:PD), as illustrated in Fig. 12.3.1.

A 28nm high-k metal-gate SRAM with Asynchronous Cross-Couple Read Assist (AC 2 RA) circuitry achieving 3x reduction on speed variation for single ended arrays

Asynchronous Cross-Couple Read Assist (AC2RA) circuitry scheme was invented for single-ended sensing to minimize speed variation in 28nm HKMG process. It improves SRAM array speed variation by 63.3% which is adequate to cover 6σ variation. Access time is also boosted by faster sensing.