Jung-Tang Huang
National Taipei University of Technology
Network
Latest external collaboration on country level. Dive into details by clicking on the dots.
Publication
Featured researches published by Jung-Tang Huang.
nano/micro engineered and molecular systems | 2011
Jung-Tang Huang; Kai-Si Chen; Chu-Che Chien
This paper presents a low-noise differential capacitive sensing circuit for omnidirectional microphone to detection accurate sound-source. The adaptive readout circuitry supports high-resolution signal acquisition from capacitive, resistive, voltage and current mode sensors. The chip was fabricated in TSMC 0.35um 2P4M CMOS process, its area is 2.31*2.39µm2, dissipates 6mW at 3.3V in a typical sensors application utilizing periodic sleep mode, and can read out a wide range of sensors with high sensitivity. The circuit includes a non-overlap clock generator and highly sensitive readout amplifier. Fully differential structure provides good noise suppression ability. And the amplifier offset can be eliminated by the Correlated Double Sampling (CDS). It achieves low noise performance while capacitors variation from 100fF to 3pF. This paper presents a circuit of tiny capacitor sensor.
international microsystems, packaging, assembly and circuits technology conference | 2010
Hou-Jun Hsu; Jung-Tang Huang; Kuo-Yu Lee; Ting-Chiang Tsai
This paper relates to the method of formation and structure of pillar bump with shape and dimension controllable, it specifically relates to a technique that uses polishing and planarization technique to let all pillar bumps have dimension and shape matching the design.
IEEE Electron Device Letters | 2014
Kuan-Ting Lin; Yu-Jen Chen; Jian-Yu Hsieh; Shuo-Hung Chang; Ying-Jay Yang; Jung-Tang Huang; Shey-Shi Lu
A gold plated carbon nanotube (CNT) bundle antenna, which is integrated with a voltage control oscillator (VCO) is reported. Gold plating reduces ohmic loss and improves radiation efficiency of the CNT antenna. Reflection measurements of the antenna show a return loss of 12 dB at 67 GHz and -6 dB impedance bandwidth at 53-87.5 GHz, 140-168 GHz, and 207-220 GHz, respectively. The VCO implemented in 65-nm CMOS technology is designed to be integrated with the antenna for the measurement of antenna gain. The measurement result of the antenna gain is -9.7 dBi at 50.7 GHz. These experimental results demonstrate that the proposed antenna is very promising for millimeter-wave applications.
international microsystems, packaging, assembly and circuits technology conference | 2012
Hou-Jun Hsu; Jung-Tang Huang; Kuo-Yu Lee; Ting-Chiang Tsai
In recent years, as mobile equipment such as cellular phones and PDAs become drastically higher performance and downsized, semiconductor devices are rapidly becoming more integrated and higher speed. As a result of high integration, the pitches of electrode pads in chips are becoming smaller than 100 μm. In some devices, pad pitches are as small as 40 μm. Because the packing density of circuits has increased, the width of the probe and the space between each probe needs to be reduced. Therefore, in the field of IC testing, probe cards that contact the I/O pads of the devices are required to have more probes arranged in higher density. In order to achieve these small probes and narrow pitch probes, the fabrication processes have been studied. Microfabrication technique can be applied to develop probe cards with high-density and high pin-count by batch processing, such as probes have been reported to be fabricated by using the LIGA (Lithographie Galvanoformung, Abformung) process, the LIGA technology is the most popular as a result of low cost and batch production. The primary fabrication processes were photolithography, electroforming, and polishing technology. The material of the electro-plated probe tip was a Ni-Co alloy. In this study, we demonstrated the potential of 30×40 um tips (φ2 mil) cobra type contact probe by UV-LIGA process. The contact force is 4±1 gf with 100 μm over drive (O.D.) and lifetime is more than 300,000 touchdowns. The measured contact resistance is less than 640 mΩ and current carrying capability is 150 mA at room temperature.
international interconnect technology conference | 2009
Hou-Jun Hsu; Jung-Tang Huang; Kuo-Yu Lee; Rung-Gen Wu; Ting-Chiang Tsai
In this paper, we report a novel plating-friendly polishing mechanism for fabrication of high coplanarity and high density lead-free copper pillar bumps for advanced packaging applications. The final experimental results showed that the UIW (Uniformity in Wafer) could be sharply decreased from 6.37% after plating to 1.7% after polishing and even to 1.7% after reflow throughout the entire 4 inch wafer.
international conference on electronic materials and packaging | 2006
Jung-Tang Huang; Yao-Yi Yang; Shey-Shi Lu; Cheng-Hung Tsai; Liang-Tse Lin; Chiu-Chin Yang
This paper explores the use of single-walled carbon nanotubes (SWCNTs) as a gas sensor for detecting organic gas molecules. A low-temperature dielectrophoresis (DEP) method is employed to combine CNTs with Transimpedance Amplifier (TIA) based on UMC 0.18 um 1P6M CMOS process into a nanosensor device.
international microsystems, packaging, assembly and circuits technology conference | 2009
Jung-Tang Huang; Po-An Lin; Po-Chin Lin; Kuo-Yu Lee; Hou-Jun Hsu
The miniaturization of components and systems has been progressing rapidly due to the developments in Micro-Electro-Mechanical (MEMS). The greatest advantage of micro injection molding is that it can massively produce micro-components rapidly with low-cost. Due to the poor flow capability of melting plastics into micro channel, and the additions of the engineering-plastics and fibers, it is difficult to inject the melted plastics into the cavities of the mold. In order to apply the microinjection technique in the fabrication of microfluidic chip, raising cavity surface temperature will be one of the solutions and reduce the cycle-time. High mold temperature not only improves the replication capacity of micro-structures but also effectively reduces molecular orientation. Therefore, developing systems for rapidly heating and cooling for injection of microfluidic chip is the main objective of this study. Numerical computations of eddy currents and heat conduction have been carried out by using the finite-element method (FEM). A simulation tool is also developed by integration of both thermal and electromagnetic analysis modules of ANSYS. Coil current, coil to plate distance and heating time are varied for both experiments and simulations. Several modifications, such as spacing in between coil turns, the distance of the workpiece and the coils, and dimensional parameters, are carried out. The capability and accuracy of simulations on the induction heating are verified from experiments, the simulated temperature distributions show reasonable agreement with measured results. To evaluate the feasibility and efficiency of induction heating on the mold surface temperature control. The size of mold plate heated by induction heating is 80×70×10 mm3. The mold plate can be rapidly heated from room temperature to about 120°C in 20 s. The simulation of the mold surface temperature with respect to time is consistent with measured results.
international conference on electronic materials and packaging | 2008
Jung-Tang Huang; Chieh-Han Lee; Chiu-Chin Yang; Kai-Yuan Jeng; Jeng Lin; Kuo-Yu Lee
This study presents a 3-Axis CMOS MEMS Accelerometer include novel post CMOS MEMS processes which is used to fabricate Z-axis capacitance accelerometer, utilizing processes combined with TSMC 0.35um 2P4M Standard CMOS Process and the method of wet etching process to etch the Aluminum metal structure in order to form the suspension structure composed of multi-layer metal and via layer. The sensing space can therefore be reached to cause displacement due to the acceleration between upper and lower electrode plates, and the change of capacitance is produced. In order to prevent interference when measuring displacement and change in capacitance, the design approach of integrating three axes into one is not adopted, but rather, the accelerations of three axes are designed separately on one chip. Moreover, integrating acceleration sensing devices with CMOS circuitries to disclose processors-inside sensing system will have advantages of low cost, compact, lower power consumption and fast measuring purposes. The primary sensing range of this accelerometer is from 1G to 10G, and as can be observed after simulation, in order to achieve enough sensitivity, when a 2G acceleration is applied in the X- and Y-axes, a displacement of 23nm will occur, and so will a change in capacitance of 80fF. Moreover, from the mode analysis, the resonant frequency of the X-axis and Y-axis accelerometer was 9.3 KHz; when a 2G acceleration is applied in the Z-axis, a displacement of 35nm and a change in capacitance of 30fF will occur, the resonant frequency of the Z-axis accelerometer was 2.8KHz.
international conference on electronic materials and packaging | 2006
Jung-Tang Huang; Kou-Yu Lee; Chan-Shoue Wu; Chung-Yi Lin; Sheng-Hsiung Shih
This paper is characterized by using MEMS process to fabricate and assemble vertical probe cards, and form their top and bottom guides in both vertical and horizontal directions simultaneously. Combining LIGA-like process with a novel CMP-like polishing process enables us to significantly promote the overall co-planarity of probe cards as exactly as within 1mum. In the assembly procedure, we mainly adopt a kind of SU8 photoresist (PR) notable for being used to coat high aspect ratio micro-structures to assemble plated probes in a row and then take them off by means of inverse electroplating technique. In terms of the design of probe guides, we design them into open comb structures with a view to getting fast assembly. Their materials could be chosen either SU8 or insulating material on metal, which features with the advantages of excellent mechanical characteristics, wear-resistance and better insulation. A space transformer made of advanced flip chip package is then employed to transform signals between printed circuit boards and probe module so that helps us hit the ultimate targets of mass production and low cost. Finally, the proposed vertical probe cards are also convenient to assemble, maintain and dismantle. Only by taking the signal converter atop on the probe cards off can we arbitrarily replace any damaged single probe with a new one when we need to change probes.
international microsystems, packaging, assembly and circuits technology conference | 2012
Hou-Jun Hsu; Jung-Tang Huang; Kuo-Yu Lee; Ting-Chiang Tsai; Chia-Hung Chou
Recently, there are many researches on the design of RF probes. Usually the materials of RF probe are tungsten and copper beryllium. They employed fabrication process of soldering and drawing of metal wire, which are not compatible with MEMS or IC fabrication process. Precise and high skill assembly is needed to finish the final probe module therefore results in high cost. This paper presents a novel RF probe module design which can be fabricated by Micro Electro Mechanical (MEM) fabrication process to reduce the cost. We use microwave simulation software, such as IE3D, Microwave Office, and Fidelity for design and analysis, and to know what kind of probe can reach the optimal impedance match and S-parameter. The design flow chart is coaxial cable to transform square coaxial cable, finally, in order to match up CPW standard pitches, therefore, design rectangular coaxial transition and success suitable ratio. Probe can match 50 Ω.