Ting-Chiang Tsai

Structure and method of forming pillar bumps with controllable shape and size

This paper relates to the method of formation and structure of pillar bump with shape and dimension controllable, it specifically relates to a technique that uses polishing and planarization technique to let all pillar bumps have dimension and shape matching the design.

Development of UV-LIGA contact probe

In recent years, as mobile equipment such as cellular phones and PDAs become drastically higher performance and downsized, semiconductor devices are rapidly becoming more integrated and higher speed. As a result of high integration, the pitches of electrode pads in chips are becoming smaller than 100 μm. In some devices, pad pitches are as small as 40 μm. Because the packing density of circuits has increased, the width of the probe and the space between each probe needs to be reduced. Therefore, in the field of IC testing, probe cards that contact the I/O pads of the devices are required to have more probes arranged in higher density. In order to achieve these small probes and narrow pitch probes, the fabrication processes have been studied. Microfabrication technique can be applied to develop probe cards with high-density and high pin-count by batch processing, such as probes have been reported to be fabricated by using the LIGA (Lithographie Galvanoformung, Abformung) process, the LIGA technology is the most popular as a result of low cost and batch production. The primary fabrication processes were photolithography, electroforming, and polishing technology. The material of the electro-plated probe tip was a Ni-Co alloy. In this study, we demonstrated the potential of 30×40 um tips (φ2 mil) cobra type contact probe by UV-LIGA process. The contact force is 4±1 gf with 100 μm over drive (O.D.) and lifetime is more than 300,000 touchdowns. The measured contact resistance is less than 640 mΩ and current carrying capability is 150 mA at room temperature.

A novel high coplanarity lead free copper pillar bump fabrication process

In this paper, we report a novel plating-friendly polishing mechanism for fabrication of high coplanarity and high density lead-free copper pillar bumps for advanced packaging applications. The final experimental results showed that the UIW (Uniformity in Wafer) could be sharply decreased from 6.37% after plating to 1.7% after polishing and even to 1.7% after reflow throughout the entire 4 inch wafer.

Analysis and design of MEMS RF probe

Recently, there are many researches on the design of RF probes. Usually the materials of RF probe are tungsten and copper beryllium. They employed fabrication process of soldering and drawing of metal wire, which are not compatible with MEMS or IC fabrication process. Precise and high skill assembly is needed to finish the final probe module therefore results in high cost. This paper presents a novel RF probe module design which can be fabricated by Micro Electro Mechanical (MEM) fabrication process to reduce the cost. We use microwave simulation software, such as IE3D, Microwave Office, and Fidelity for design and analysis, and to know what kind of probe can reach the optimal impedance match and S-parameter. The design flow chart is coaxial cable to transform square coaxial cable, finally, in order to match up CPW standard pitches, therefore, design rectangular coaxial transition and success suitable ratio. Probe can match 50 Ω.

Fabrication technology of CMOS-MEMS probe chip compatible with electroless nickel plating process

In this study, we use the standard TSMC 0.35 μm 2P4M process to design CMOS-MEMS probe chip. MEMS technology involves the following steps such as lithography process, electroless nickel (EN) plating process, grinding process and dry etching process. The probe chip has through silicon via (TSV) package structure, and the combination of CMOS process within the multi-layer interconnections, which could assist the connection between the probes head the external devices, and reduce the difficulty of wiring layout. In addition, passive components or circuits could be integrated with the CMOS chip to improve the frequency bandwidth and measuring quality. So far, MEMS probe exist a shortcomings that are not able to be integrated with the CMOS process, and the testing cost. The finite element method was adapted to design of probe shapes and sizes. The LIGA-like thick photoresist process and EN plating technique was used in this study, Ni-P alloy to increase the thickness of the cantilever probe to strengthen its support strength were also applied. When the probe cantilever through the EN plating of deposition time, the uneven surface was appeared, each layer structure is used by polishing process to achieve the surface coplanarity. Finally, the probes structure were suspended by the dry etching process (RIE, ICP-RIE), and this study successfully fabricated chips forming one of the probe.

High Coplanarity and Fine Pitch Copper Pillar Bumps Fabrication Method

In this paper, we report a novel plating-friendly polishing mechanism for fabrication of high coplanarity and high density lead-free copper pillar bumps for advanced packaging applications. The final experimental results showed that the uniformity in wafer (UIW) could be sharply improved from 4.31% after plating to 2.88% after polishing and even to 2.54% after reflow throughout the entire 4 inch wafer.

Common platform for packaging micromachined devices

This paper presents a common platform for packaging micromachined devices, such as motion sensors, microphones, actuator RF switches etc. The method utilizes the semiconductor process, MEMS technique and Electroless technique to build the CMOS-MEMS chip and the second chip, which are then bonded together face to face. Herein, the second chip can further contain Micro Controller Unit (MCU) or antenna system, which can efficiently enhance the performances of CMOS-MEMS sensor without occupying extra packaging area and increasing the process cost. Moreover, the second chip is designed to a common platform which can serve different size or several micromachined components of CMOS-MEMS chip in a single platform.

Design and fabrication of low-insertion loss and high-isolation CMOS-MEMS switch for microwave applications

This paper presents a design of RF MEMS contact switch with high isolation, low insertion loss, small chip area and low power consumption. The switch is fabricated by standard 1P6M 0.18μm CMOS process from TSMC which is compatible with CMOS process. A dc-bias voltage is applied between the cantilever beam and bottom electrode. The switch is actuated by electrostatic force that drove the tail of the cantilever beam contact with the transmission line. In order to avoid RF signal loss, DC and RF signal are separated by SiO2. The simulation results show that SiO2 can effectively avoid RF signal loss. The spring structure of cantilever can effectively reduce the driving voltage and improve residual stress (used by the warpage problem.) The cantilever structure of switch is based on aluminum and the scarified layer is used by the aluminum and silicon oxide. RIE etching was applied to remove the scarified layer of silicon oxide to form wet etching channels. So, the structure was easy to be released by wet-etching. At last, the supercritical CO2 drying was used to release the structure (annoying stiction problem.) Finally, we successfully demonstrate the fabrication of RF MEMS contact switch by standard 1P6M 0.18μm CMOS process from TSMC. Also, the post-processing is implemented to manufacture the RF MEMS contact switch. The proposed RF MEMS contact switch can be used in microwave CMOS RF front-ends where multiband functionality and reconfigurability is required. The measurement results as below, the pull-in voltage of RF MEMS contact switch is 2.8V, isolation is −60dB, respectively. Since the CMOS silicon has a very low resistivity (8Ω • cm), it will increase the isolation of RF MEMS contact switch. So, the Metal_1 layer is designed as ground which could greatly improve isolation.

Carbon nanotube-based sensor Device compatible with the CMOS process

The invention disclosed a method for integrating CMOS circuit chips with carbon nanotubes (CNTs) as low-temperature sensor device. The method comprises opening the passivation-layer on the CMOS chips surface to expose the metal layers, sputtering or evaporating a gate oxide film on the metal layers, coating a self-assembled monolayer of 3-aminopropyltriethoxysilane solution on the gate oxide film for the purpose to immobilize the carbon nanotubes and form a sensing platform, using photolithographic method and then sputtering or evaporating to define the source and drain electrodes on the chips surface.

Fabrication Technology of Microelectromechanical Systems Probe Chip Compatible with Standard Complementary Metal–Oxide–Semiconductor Process

In this paper, we present a microelectromechanical systems (MEMS) probe chip compatible with the standard complementary metal–oxide–semiconductor (CMOS) process for testing RF devices and bumps. Using the standard CMOS process to fabricate in advance the multilayer interconnections between metal layers can conveniently facilitate the layout of the space transformer. In a limited area, we design two probe structures of meander shape and spiral shape. The probe cantilever consists of a CMOS membrane and the probe pitch is 150 µm. The probe tip is fabricated successfully by electroless nickel (EN) plating process and the height of the probe tip approaches 106 µm. In particular, grinding and polishing processes are employed to level the rough surface of the probe tip so as to obtain uniform coplanarity. Moreover, in the photoresist SU-8 removal process, the plasma removal process is used instead of the stripper solutions to protect the probe tip from being damaged. The meander shape and spiral shape of probe cantilevers are successfully suspended by an inductively coupled plasma (ICP) etch system and the probe cantilevers have no warpage.