Jung Uk Cho

FPGA Design and Implementation of a Real-Time Stereo Vision System

Stereo vision is a well-known ranging method because it resembles the basic mechanism of the human eye. However, the computational complexity and large amount of data access make real-time processing of stereo vision challenging because of the inherent instruction cycle delay within conventional computers. In order to solve this problem, the past 20 years of research have focused on the use of dedicated hardware architecture for stereo vision. This paper proposes a fully pipelined stereo vision system providing a dense disparity image with additional sub-pixel accuracy in real-time. The entire stereo vision process, such as rectification, stereo matching, and post-processing, is realized using a single field programmable gate array (FPGA) without the necessity of any external devices. The hardware implementation is more than 230 times faster when compared to a software program operating on a conventional computer, and shows stronger performance over previous hardware-related studies.

Fpga-based face detection system using Haar classifiers

This paper presents a hardware architecture for face detection based system on AdaBoost algorithm using Haar features. We describe the hardware design techniques including image scaling, integral image generation, pipelined processing as well as classifier, and parallel processing multiple classifiers to accelerate the processing speed of the face detection system. Also we discuss the optimization of the proposed architecture which can be scalable for configurable devices with variable resources. The proposed architecture for face detection has been designed using Verilog HDL and implemented in Xilinx Virtex-5 FPGA. Its performance has been measured and compared with an equivalent software implementation. We show about 35 times increase of system performance over the equivalent software implementation.

An FPGA-Based Multiple-Axis Motion Control Chip

This paper presents the design and implementation of a multiple-axis motion control chip using a field-programmable gate array (FPGA). This multiple-axis motion control chip is designed to control a multiple-axis motion system such as a robotic arm manipulator or a computer numerical control machine. The proposed motion control chip has many functions. These include velocity profile generation, interpolation calculation, inverse kinematics calculation, proportional-integral-derivative control, feedback count, pulse integration, data conversion, clock generation, and external interfacing. These functions are designed using the VHSIC hardware description language and implemented on an FPGA according to the electronic design automation design methodology. This allows for a highly sampled, accurate, flexible, compact, low-power, and low-cost motion control system. The detailed design of the proposed motion control chip is presented. A multiple-axis motion control system using this chip is implemented, and its performance is measured. The multiple-axis motion control system is implemented on a platform consisting of a chip-based multiple-axis motion controller, analog ac servo drivers, a selective compliant assembly robot arm robot, and a host personal computer.

A Real-Time Object Tracking System Using a Particle Filter

Particle filters have attracted much attention due to their robust tracking performance in cluttered environments. Particle filters maintain multiple hypotheses simultaneously and use a probabilistic motion model to predict the position of the moving object, and this constitutes a bottleneck to the use of particle filtering in real-time systems due to the expensive computations required. In order to track moving objects in real-time without delay and loss of image sequences, a particle filter algorithm specifically designed for a circuit and the circuit of the object tracking algorithm using the particle filter are proposed. This circuit is designed by VHDL (VHSIC hardware description language), and implemented in an FPGA (field programmable gate array). All of the functions of the proposed particle filter used to track moving objects are implemented in the FPGA. The object tracking system employing this circuit is implemented and then its performance is measured

Parallelized Architecture of Multiple Classifiers for Face Detection

This paper presents a parallelized architecture of multiple classifiers for face detection based on the Viola and Jones object detection method. This method makes use of the AdaBoost algorithm which identifies a sequence of Haar classifiers that indicate the presence of a face. We describe the hardware design techniques including image scaling, integral image generation, pipelined processing of classifiers, and parallel processing of multiple classifiers to accelerate the processing speed of the face detection system. Also we discuss the parallelized architecture which can be scalable for configurable device with variable resources. We implement the proposed architecture in Verilog HDL on a Xilinx Virtex-5 FPGA and show the parallelized architecture of multiple classifiers can have 3.3× performance gain over the architecture of a single classifier and an 84× performance gain over an equivalent software solution.

FPGA-based real-time visual tracking system using adaptive color histograms

Visual tracking using a color feature is based on pattern matching algorithms where the appearance of the target is compared with a reference model in successive images and the position of the target is estimated. The major drawback of these methods is that such operations are usually considered at the top level of image processing both due to the datas intrinsic complexity and to the high computational cost associated with a solution in real time. The probabilistic tracking methods have been shown to be robust and versatile for a modest computational cost. However, the probabilistic tracking methods break down easily when the object moves very fast because these methods search only the regions of interest (ROIs) based on the probability density function (pdf) to estimate the position of the moving object. In this paper, we propose a real-time visual tracking circuit using adaptive color histograms. We propose a window- based image processing structure to improve the processing speed of the visual tracking circuit. The visual tracking circuit searches all regions of the image to perform a matching operation in order to estimate the position of the moving object. The main results of our work are that we have designed and implemented a physically feasible hardware circuit to improve the processing speed of the operations required for real-time visual tracking. Therefore, this work has resulted in the development of a real-time visual tracking system employing an FPGA (field programmable gate array) implemented circuit designed by VHDL (the VHSIC hardware description language). Its performance has been measured to compare with the equivalent software implementation.

Multiple Objects Tracking Circuit using Particle Filters with Multiple Features

Object tracking is a challenging problem in a number of computer vision applications. A number of approaches have been proposed and implemented to track moving objects in image sequences. The particle filter, which recursively constructs the posterior probability distributions of the state space, is the most popular approach. In the particle filter, many kinds of features are used for tracking a moving object in cluttered environments. The specific feature for tracking is selected according to the type of moving object and condition of the tracking environment. Improved tracking performance is obtained by using multiple features concurrently. This paper proposes the particle filter algorithm, using multiple features, such as IFD (inter-frame difference) and gray level, to track a moving object. The IFD is used to detect an object and the gray level is used to distinguish the target object from other objects. This paper designs the circuit of the proposed algorithm using VHDL (VHSIC hardware description language) in an FPGA (field programmable gate array) for tracking without considerable computational cost, since the particle filter requests many computing powers to track objects in real-time. All functions of the proposed tracking system are implemented in an FPGA. A tracking system with this FPGA is implemented and the corresponding performance is measured

Application of Velocity Profile Generation and Closed-Loop Control in Step Motor Control System

Step motors are widely used in motion control systems. The step motor controller must perform high-precision positioning and smooth movement operation. In motion systems applying velocity profile control, the velocity of the motor gradually increases or decreases, to avoid the negative effect caused by the sudden change in velocity. Previous research proposes several step motor controller designs, that contain several modules, including a velocity profile generator, step motor driver, and feedback counter. These controllers are able to perform precise positioning and provide smooth motion operation. However, because these controllers operate in an open-loop control so the synchronous condition can be lost when disturbances in load torque exist. This paper presents the application of closed-loop control in the step motor controller. The control algorithm is based on two mode operations: open-loop and closed-loop. The controller operates in open-loop mode when it remains synchronized, and switches to closed-loop mode when it loses synchronization. This paper presents an algorithm for generating various velocity profiles and closed-loop control algorithms. The experiment is performed on a 16-b DSP, to verify the performance of the design. The experimental results show a velocity profile of unsymmetrical shape and demonstrate effective closed-loop control in an actual step motor system

Object Tracking Circuit using Particle Filter with Multiple Features

Object tracking is a challenging problem in a number of computer vision applications. A number of approaches have been proposed and implemented to track moving objects in image sequences. The particle filter, which recursively constructs the posterior probability distributions of the state space, is the most popular approach. In the particle filter, many kinds of features are used for tracking a moving object in cluttered environments. The specific feature for tracking is selected according to the type of moving object and condition of the tracking environment. Improved tracking performance is obtained by using multiple features concurrently. This paper proposes the particle filter algorithm, using multiple features, such as IFD (inter-fame difference) and gray level, to track a moving object. The IFD is used to detect an object and the gray level is used to distinguish the target object from other objects. This paper designs the circuit of the proposed algorithm using VHDL (VHSIC hardware description language) in an FPGA (field programmable gate array) for tracking without considerable computational cost, since the particle filter requests many computing powers to track objects in real-time. All functions of the proposed tracking system are implemented in an FPGA. A tracking system with this FPGA is implemented and the corresponding performance is measured

Energy benefits of reconfigurable hardware for use in underwater snesor nets

Small, dense underwater sensor networks have the potential to greatly improve undersea environmental and structural monitoring. However, few sensor nets exist because commercially available underwater acoustic modems are too costly and energy inefficient to be practical for this applications. Therefore, when designing an acoustic modem for sensor networks, the designer must optimize for low cost and low energy consumption at every level, from the analog electronics, to the signal processing scheme, to the hardware platform. In this paper we focus on the design choice of hardware platform: digital signal processors, microcontrollers, or reconfigurable hardware, to optimize for energy efficiency while keeping costs low. We implement one algorithm used in an acoustic modem design - Matching Pursuits for channel estimation - on all three platforms and perform a design space exploration to compare the timing, power and energy consumption of each implementation. We show that the reconfigurable hardware implementation can provide a maximum of 210X and 52X decrease in energy consumption over the microcontroller and DSP implementations respectively.