Jung-Woong Park

High-speed CMOS Frequency Divider with Inductive Peaking Technique

This work proposes an integrated high frequency divider with an inductive peaking technique implemented in a current mode logic (CML) frequency divider. The proposed divider is composed with a master-slave flip-flop, and the master-slave flip-flop acts as a latch and read circuits which have the differential pair and cross-coupled n-MOSFETs. The cascode bias is applied in an inductive peaking circuit as a current source and the cascode bias is used for its high current driving capability and stable frequency response. The proposed divider is designed with 0.18-μm CMOS process, and the simulation used to evaluate the divider is performed with phase-locked loop (PLL) circuit as a feedback circuit. A divide-by-two operation is properly performed at a high frequency of 20 GHz. In the output frequency spectrum of the PLL, a peak frequency of 2 GHz is obtained witha divide-by-eight circuit at an input frequency of 250 MHz. The reference spur is obtained at -64 dBc and the power consumption is 13 mW.

Electrical Characteristic of Power MOSFET with Zener Diode for Battery Protection IC

A high power MOSFET switch based on a 0.35 μm CMOS process has been developed for the protection IC of a rechargeable battery. In this process, a vertical double diffused MOS (VDMOS) using 3 μm-thick epi-taxy layer is integrated with a Zener diode. The p-n+ Zener diode is fabricated on top of the VDMOS and used to protect the VDMOS from high voltage switching and electrostatic discharge voltage. A fully integrated digital circuit with power devices has also been developed for a rechargeable battery. The experiment indicates that both breakdown voltage and leakage current depend on the doping concentration of the Zener diode. The dependency of the breakdown voltage on doping concentration is in a trade-off relationship with that of the leakage current. The breakdown voltage is obtained to exceed 14 V and the leakage current is controlled under 0.5 μA. The proposed integrated module with the application of the power MOSFET indicates the high performance of the protection IC, where the overcharge delay time and detection voltage are controlled within 1.1 s and 4.2 V, respectively.

High Performance Charge Pump Converter with Integrated CMOS Feedback Circuit

In this paper, an integrated low-voltage control circuit is introduced for a charge pump DC-DC boost converter. By exploiting the advantage of the integration of the feedback control circuit within CMOS technology, the charge pump boost converter offers a low-current operation with small ripple voltage. The error amplifier, comparator, and oscillator in the control circuit are designed with the supply voltage of 3.3 V and the operating frequency of 1.6~5.5 MHz. The charge pump converter with the 4 or 8 pump stages is measured in simulation. The test in the 0.35 μm CMOS process shows that the load current and ripple ratio are controlled under 1 mA and 2% respectively. The output-voltage is obtained from 4.8 ~ 8.5 V with the supply voltage of 3.3 V.

High performance two-stage charge-pump for spur reduction in CMOS PLL

This paper proposes a charge pump that minimizes the current mismatch and keeps the constant current across a wide range of output voltage. The charge pump is a two-stage circuit which is composed of the conventional push-pull charge pump and the compensation circuit. The compensation circuit has a feedback biasing circuit and an op-amp to act as a voltage follower. The features of feedback circuit and voltage follower are the important elements to reduce the current mismatch. The proposed charge pump is applied in 2 GHz PLL to check out the noise spectrum of the spur and phase offset which are occurred from the current mismatch. The proposed charge pump indicates that the current mismatch is less than 5 % over the voltage range of 0.30 ~ 1.45 V which covers almost 63 % of the 1.8 V supply voltage. The spur in PLL is obtained to be -63.7 dBc, while the conventional charge pump provides the spur of -36.2 dBc in the same PLL.

Integrated High Speed Current-Mode Frequency Divider with Inductive Peaking Structure

In this paper, a high performance current mode logic (CML) frequency divider is introduced in an integrated CMOS phase-locked loop (PLL). Inductive peaking structure and cascode circuit are applied in the CML frequency divider to obtain the broad-band and high frequency operation. In order to obtain a stable operation with low power, the resistor in the inductive peaking structure is replaced by the cascode circuit. DC bias voltage is applied in MOS gate as a current source in the divider. The proposed frequency divider is applied in the conventional PLL which is integrated with 0.18 μm CMOS process. Simulation test shows that the 2:1 divider is operated at the input frequency of 20 GHz with the power consumption of 15 mW.

Latch-Controlled Current Cell for Low Power Current-Steering D/A Converter

This paper introduces the design and implementation of a novel current cell in current-steering digital-to-analog converter (DAC). The current cell consists of current switch and source which are independently controlled by latch. A sequential switch-on process similar to thermometer decoding is implemented in source to reduce the power consumption. A 12-b DAC has been fabricated using a single-poly four-metal 0.35 μm CMOS process. Comparison with conventional DAC shows that the proposed DAC produces a power reduction in the order of 35% without degradation of linearity.

Integration of CMOS Logic Circuits with Lateral Power MOSFET

This paper describes the CMOS logic circuit which is composed with LDMOSFET. Compared to a conventional MOSFET, the proposed LDMOSFET is considered to show a high power tolerance in CMOS inverter circuit and be well adaptable in display driver circuits which require high breakdown voltage and trans-conductance. The channel in LDMOSFET encloses a junction-type source and is an important parameter for determining the transfer characteristics of CMOS inverter. Electrical characteristics of CMOS inverter with LDMOSFETs are studied by using TCAD MEDICI simulator. The voltage transfer characteristics and on-off switching properties are examined. The digital logic levels of the output voltages are analyzed from the transfer curves and circuit operation. The high and low logic voltages show a strong dependency on the channel doping concentration. The CMOS circuit in a display driver circuit shows a large power handling capability with low ON conductance.

Low Power 20-GHz Current-Mode Frequency Divider in 0.18-um CMOS Phase-Locked Loop

This paper proposes a high performance current mode logic (CML) frequency divider for an integrated analog phase-locked loop (PLL). The frequency divider includes the inductive peaking structure with the cascode circuit. In order to obtain a high speed circuit with stable frequency response, the resistor in the inductive peaking structure is replaced by the cascode circuit which is operated by DC bias voltage in MOS gate. The proposed frequency divider is applied to the feedback circuit of an analog PLL with 0.18 µm CMOS process. Simulation shows that the six stages of 2:1 divider provide the expected frequency characteristics at the input frequency of 20 GHz. The power consumption of the proposed divider is obtained to be 6.9 mW.

Charge pump regulation with integrated 0.35 µm CMOS control circuit

This paper introduces the design of charge pump DC-DC boost converter with integrated low-voltage control circuit. By exploiting the advantage presented by the integration of both charge pump and control circuit within same CMOS technology, the DC-DC boost converter offers a low-power operation with a proper regulation. The error amplifier, comparator, and oscillator in the control circuit are designed with the supply voltage of 3.3V and the operating frequency of 5.5 MHz. The compensator circuit exploits pole-zero compensation for a stable operation. The power converter is measured in simulation. The test in 0.35 μm CMOS process shows that the output transient time of the compensator is controlled within 10 μsec and the output-voltage is accurately controlled from 4 ~ 10 V with a small load current within 1 mA.