Ho-Yong Choi

A low‐power CMOS DC‐DC buck converter with on‐chip stacked spiral inductor

Purpose – The purpose of this paper is to present a fully integrated power converter. A stacked spiral inductor is applied in a voltage‐mode CMOS DC‐DC converter for the chip miniaturization and low‐power operation.Design/methodology/approach – The three‐layer spiral inductor is simulated with an equivalent circuit and applied to the DC‐DC converter. The DC‐DC buck converter has been fabricated with a standard 0.35 μm CMOS process. The power converter is measured in both experiment and simulation in terms of frequency and electrical characteristics.Findings – Experimental results show that the converter with the stacked spiral inductor operates properly with the inductance of 7.6 nH and mW power range. The measured inductance of the stacked spiral inductor is found to be almost half of the circuit designed value because of the parasitic resistances and capacitances in the spiral inductor.Originality/value – This paper first introduces the application of the integrated stacked spiral inductor in DC‐DC buck...

A sequential triggering technique in cascaded current source for low power 12‐b D/A converter

Purpose – The purpose of this paper is to introduce a low power digital‐to‐analog converter (DAC) by using a sequential triggering technique in cascaded current source.Design/methodology/approach – The block of current cell consists of current switch and source. A sequential switching on process is implemented with the current triggering technique in source. An experiment of 12‐b 150‐MS/s DAC has been integrated in a single‐poly four‐metal 0.35 μm CMOS process.Findings – Compared with conventional cell array in 12‐b 150‐MS/s DAC, the proposed cell array shows that more than 30 percent of power consumption is reduced in full digital bit operation with allowable linearity error of 0.4 LSB.Originality/value – This paper presents a new operation method of cell array in a current‐steering digital‐to‐analog converter (DAC) to reduce the power consumption significantly.

Application of cascode level shifter for EMI reduction in LCD driver IC

Purpose – This paper aims to design the circuit for electromagnetic interface (EMI) reduction in liquid crystal display (LCD). Design/methodology/approach – The cascode level shifter and segmented driver circuit are applied in LCD column driver integrated circuit (IC) for EMI reduction. Cascode current mirror is used in the proposed level shifter for DC voltage biasing and reduction of the driving current which passes through the level shifter. The on-off switching currents and transient times are measured and compared between the conventional and proposed level shifters. Additionally, a segmented data latch is obtained by the timing spread solution in data latch, and applied to split the large peak switching current into a number of smaller peak current. The timing spread-operation does not actually reduce the total power of the noise, instead, it spreads the noise power evenly over the frequency bandwidth. The optimal number of latch is dependent on the operating frequency and EMI allowance. The column ...

High Performance Charge Pump Converter with Integrated CMOS Feedback Circuit

In this paper, an integrated low-voltage control circuit is introduced for a charge pump DC-DC boost converter. By exploiting the advantage of the integration of the feedback control circuit within CMOS technology, the charge pump boost converter offers a low-current operation with small ripple voltage. The error amplifier, comparator, and oscillator in the control circuit are designed with the supply voltage of 3.3 V and the operating frequency of 1.6~5.5 MHz. The charge pump converter with the 4 or 8 pump stages is measured in simulation. The test in the 0.35 μm CMOS process shows that the load current and ripple ratio are controlled under 1 mA and 2% respectively. The output-voltage is obtained from 4.8 ~ 8.5 V with the supply voltage of 3.3 V.

Integrated high voltage boost converter with LC filter and charge pump

Purpose – The paper aims to design of dual-mode boost converter with integrated low-voltage control circuit is introduced in this paper. The paper aims to discuss these issues. Design/methodology/approach – The converter is operated either with LC filter or with charge pump circuit by the switch control. The control stage with error amplifier, comparator, and oscillator is designed with the supply voltage of 3.3 V and the operating frequency of 5.5 MHz. The compensator circuit exploits a pole compensation for a stable operation. Findings – The simulation test in 0.35 μm CMOS process shows that the charge pump regulator and DC-DC boost converter are accurately controlled with the variation of number of stages and duty ratio. The output-voltage is obtained to be 6-15 V within the ripple ratio of 5 percent. Maximum power consumption is about 0.65 W. Originality/value – This dual-mode is useful in the converter with a wide load-current variation. The advantage of the dual-mode converter is that it can be used...

Low Power 8-b CMOS Current Steering Folding-Interpolating A/D Converter

This paper presents a CMOS A/D converter based on the folding and interpolating technique. A current steering folder composed of differential pairs allows low power operation and an interpolation is used for high speed with low supply voltage. In a folding circuit, only twenty-three MOSFETs are required to have eight reference voltages of an 8-b A/D converter. The interpolation is implemented with a current division technique to generate 32 folding signals. This approach requires much less area and power consumption than other conventional flash A/D converter. The simulation in a 0.35μm CMOS process achieves 8-b resolution at 250 Msample/s with power consumption 70mW at 3.3V power supply. The preliminary experiment indicates the current steering folder and coarse bits operate as expected.

High performance two-stage charge-pump for spur reduction in CMOS PLL

This paper proposes a charge pump that minimizes the current mismatch and keeps the constant current across a wide range of output voltage. The charge pump is a two-stage circuit which is composed of the conventional push-pull charge pump and the compensation circuit. The compensation circuit has a feedback biasing circuit and an op-amp to act as a voltage follower. The features of feedback circuit and voltage follower are the important elements to reduce the current mismatch. The proposed charge pump is applied in 2 GHz PLL to check out the noise spectrum of the spur and phase offset which are occurred from the current mismatch. The proposed charge pump indicates that the current mismatch is less than 5 % over the voltage range of 0.30 ~ 1.45 V which covers almost 63 % of the 1.8 V supply voltage. The spur in PLL is obtained to be -63.7 dBc, while the conventional charge pump provides the spur of -36.2 dBc in the same PLL.

Circuit design for broad band EMI reduction in LCD driver IC

In this paper, the circuit for electromagnetic interface (EMI) reduction in liquid crystal display (LCD) is proposed. The segmented driver circuit and cascode level shifter are employed in the column driver IC for the EMI reduction. The proposed column driver IC reduces the switching peak current in LCD panel by adopting the segmented operation in data latch. It provides an oscillating transient current with significantly reduced peak currents. The column driver IC and clock controller are integrated in 0.35 μm CMOS technology with 1-poly and 4-metal process. The simulation test shows that the proposed column driver circuit for LCD driver IC significantly reduces EMI noise level by more than 15 dB with 20 segmented operation in data latch at 40 MHz frequency.

Low Power 20-GHz Current-Mode Frequency Divider in 0.18-um CMOS Phase-Locked Loop

This paper proposes a high performance current mode logic (CML) frequency divider for an integrated analog phase-locked loop (PLL). The frequency divider includes the inductive peaking structure with the cascode circuit. In order to obtain a high speed circuit with stable frequency response, the resistor in the inductive peaking structure is replaced by the cascode circuit which is operated by DC bias voltage in MOS gate. The proposed frequency divider is applied to the feedback circuit of an analog PLL with 0.18 µm CMOS process. Simulation shows that the six stages of 2:1 divider provide the expected frequency characteristics at the input frequency of 20 GHz. The power consumption of the proposed divider is obtained to be 6.9 mW.