Jungwook Lim

Metal-insulator transition-induced electrical oscillation in vanadium dioxide thin film

In this letter, we report an observation of room temperature electrical oscillation in vanadium dioxide (VO2), a representative strongly correlated material showing a metal-insulator transition. An electric circuit for the oscillation is simply composed of a voltage source and two-terminal VO2 thin film device serially connected with a standard resistor. The systematic procedures where the oscillation occurred were explained based on the electrical relationship between the VO2 device and resistor, and the generation window of the oscillation was determined. In particular, the oscillation frequency could be controlled by adjusting an external voltage and increased up to >0.5MHz.

1/f noise in Si/sub 0.8/Ge/sub 0.2/ pMOSFETs under Fowler-Nordheim stress

The 1/f noise in Si/sub 0.8/Ge/sub 0.2/ pMOSFETs was found to be lower than in all-silicon (Si) pMOSFETs, before and after Fowler-Nordheim (F-N) stress. The minimum noise in the Si/sub 0.8/Ge/sub 0.2/ pMOSFET occurred at the thinnest unconsumed Si-cap of approximately 2 nm, because of the reduced-oxide trap density (N/sub ot/) near the Fermi level (E/sub F/) in the device. However, all samples in this study, including the Si control and the Si/sub 0.8/Ge/sub 0.2/ pMOSFETs with different unconsumed Si-cap thicknesses of 21-64 /spl Aring/, revealed almost identical relative changes in 1/f noise due to the stress, despite the relatively wide range of initial noise values. This suggests identical relative changes in N/sub ot/ at the E/sub F/ in the devices during F-N stress.

Electrical characteristics of ZrO2 gate dielectric deposited on ultrathin silicon capping layer for SiGe metal-oxide-semiconductor device applications

The electrical characteristics of ZrO2 were investigated relative to its use in SiGe metal-oxide-semiconductor (MOS) gate dielectric applications. Compared to ZrO2 directly deposited on SiGe, ZrO2, when deposited on a silicon capping layer shows a significant improvement in electrical characteristics such as low leakage current, negligible hysteresis, less fixed charge density and a lower interface state density (Dit) after low-temperature wet vapor annealing. The improvement in the electrical characteristics of ZrO2, with a silicon capping layer can be attributed to the negligible Ge segregation and surface roughness at the interface. Based on an Auger electron spectroscopy (AES) depth profile of Ge, we were able to confirm that Ge is segregated at the interface.

Fabrication of Nano-Gap Electrode Pairs Using Atomic-Layer-Deposited Sacrificial Layer and Shadow Deposition

We propose a new fabrication process of nano-gap electrode pairs using an atomic-layer-deposited (ALD) sacrificial layer and the shadow deposition technique. In this process, gap width can be precisely controlled by the number of deposition cycles of the ALD process, whereas junction area is defined by the deposition angle of the second electrode material through an overhanging shadow mask on top of the first electrode. In comparison with our previous method, process reliability has been highly improved because the unintentional deposition of the second electrode material on the sidewall of the first electrode is completely prevented. We have fabricated 10 ×10 arrays of n-type polycrystalline silicon (n-poly-Si)/Au nano-gap electrode pairs with gap widths of 6 and 9 nm, which show good insulating properties at room temperature.