Junichi Hattori

Fully coupled 3-D device simulation of negative capacitance FinFETs for sub 10 nm integration

Performances of negative capacitance FinFETs (NC-FinFETs) at sub 10 nm gate length are analyzed with a newly developed technology computer-aided design (TCAD) simulation. This simulation fully couples the Landau-Khalatnikov (L-K) equation with the physical equations for FinFETs in 3-D. It reveals an excellent immunity against short-channel effects in NC-FinFETs owing to NC-enhancement by the gate-to-drain coupling, for the first time. NC-FinFETs with a gate length of 10 nm are projected to operate with more than 26 times energy-efficiency of conventional FinFETs.

Demonstrating performance improvement of complementary TFET circuits by I on enhancement based on isoelectronic trap technology

We improved the performance of a complementary circuit comprising Si-based tunnel field-effect transistors (TFETs) by using isoelectronic trap (IET) technology. IET technology was found to increase the ON current (ION) 5 times in P-TFETs and 2 times in N-TFETs. The ION enhancement improved the inverter performance. In addition, ring oscillator (RO) circuit operation with the complementary TFET inverters was experimentally demonstrated for the first time. The RO circuit with IET-TFETs exhibited a higher operation frequency than that with conventional TFETs. IET technology provides a breakthrough towards realizing complementary circuits with Si-TFETs.

Corrugated Si nanowires with reduced thermal conductivity for wide-temperature-range thermoelectricity

We fabricated suspended straight and corrugated Si nanowires (NWs) from 55 nm thick Si-on-insulator and studied their thermal conductivity using Raman mapping. We demonstrate that corrugations induce 60%–70% reduction in NW thermal conductivity at temperatures 300–400 K. This proves the significance of ballistic phonon transport at these temperatures in sufficiently thin Si NWs and the efficiency of corrugations in thermal conductivity reduction for application in thermoelectricity. The experimental results presented here are in agreement with our NW thermal conductance calculation taking into account the effect of corrugations on low-frequency acoustic phonon branches.

Material and device engineering in fully depleted silicon-on-insulator transistors to realize a steep subthreshold swing using negative capacitance

This paper discusses material and device engineering in field-effect transistors (FETs) with HfO2-based ferroelectric gate insulators to attain a precipitous subthreshold swing (SS) by exploiting negative capacitance. Our physical analysis based on a new concept of a negative dielectric constant reveals that fully depleted silicon-on-insulator (FD-SOI) channels with a modest remnant polarization P r (3 µC/cm2 at most) are more suitable for realizing SS < 60 mV/decade than a higher P r of 10 µC/cm2, which is commonly reported for HfO2-based ferroelectric materials. We also confirm SS < 60 mV/decade in more than 5 orders of the subthreshold current in FD-SOI FETs with ferroelectric HfO2 gate insulators by device simulation.

Structural advantages of silicon-on-insulator FETs over FinFETs in steep subthreshold-swing operation in ferroelectric-gate FETs

In this paper, we discuss the subthreshold operation of fully depleted silicon-on-insulator FETs (SOI-FETs) and FinFETs, with embedded ferroelectric negative-capacitance gate insulators, using technology computer-aided design simulations. SOI-FETs with ultrathin buried-oxide layers and appropriate workfunctions for bottom electrodes are found to be more preferable to attain steep subthreshold swings lesser than 60 mV/decade, because SOI-FETs can effectively enable a voltage drop in the ferroelectric layer, even though the degree of matching of the depletion capacitance and the ferroelectric gate insulator capacitance is almost the same in SOI-FETs and FinFETs. These results give a novel insight into how the subthreshold swing can be improved in ferroelectric-gate MOSFETs.

Steep switching in trimmed-gate tunnel FET

We propose a tunnel field-effect transistor (TFET) having a trimmed gate (TG) structure, which considerably improves the subthreshold swing (SS). The TG structure truncates the needless long band-to-band tunneling (BTBT) paths to a “channel”, which normally appear in a conventional TFET, and realize a sudden switching to the on-state arising from a short BTBT path. Our simulations demonstrate that the TG-TFET can achieve an extremely steep SS, less than 10 mV/decade, in the double-gated Si-channel configuration. The TG structure also improves the ratio ION/IOFF to a value higher than that of ideal MOSFETs in the operation voltage range up to 0.35 V. The mechanism of steep switching is based on a simple modification of the gate electrostatic control; therefore, in addition to the demonstrated TFETs, the TG structure is universally applicable to many types of TFETs.We propose a tunnel field-effect transistor (TFET) having a trimmed gate (TG) structure, which considerably improves the subthreshold swing (SS). The TG structure truncates the needless long band-to-band tunneling (BTBT) paths to a “channel”, which normally appear in a conventional TFET, and realize a sudden switching to the on-state arising from a short BTBT path. Our simulations demonstrate that the TG-TFET can achieve an extremely steep SS, less than 10 mV/decade, in the double-gated Si-channel configuration. The TG structure also improves the ratio ION/IOFF to a value higher than that of ideal MOSFETs in the operation voltage range up to 0.35 V. The mechanism of steep switching is based on a simple modification of the gate electrostatic control; therefore, in addition to the demonstrated TFETs, the TG structure is universally applicable to many types of TFETs.

Simulation of GaN MOS capacitance with frequency dispersion and hysteresis

C-F curves of GaN MOS capacitors are analyzed by transient-mode semiconductor device simulation. Problems of numerical convergence in the device simulation caused by the wide range time scales of the deep level trap physics are solved by a new discretization scheme of the trap formula that takes into account the dynamic change of their ionization rates. Consequently, frequency dispersions, hysteresis characteristics, and other non-ideal characteristics of C-F curves are stably obtained for various conditions. The present method could be a strong analysis tool, providing detail trap information when compared to a wide range of C-F measurements of GaN MOS capacitors. The present method is not restricted to GaN, and is applicable to MOS capacitors or other characteristics of other semiconductor materials suffering influences of the deep level traps.

Design and simulation of steep-slope silicon-on-insulator FETs using negative capacitance: Impact of buried oxide thickness and remnant polarization

This paper discusses the importance of determining a suitable value of the buried oxide (BOX) thickness and remnant polarization in ferroelectric silicon-on-insulator FETs to attain a steep subthreshold swing (SS) by exploiting the negative capacitance effects. We reveal that a small value of remnant polarization Pr (3 μC/cm2 at most) and ultrathin BOX (<; 10 nm) are key to realizing SS <; 60 mV/decade.

A moving mesh method for device simulation

A moving mesh method for semiconductor device simulation is developed which effectively compromises accuracies without increasing mesh number. In this method, mesh positions are shifted referring to the solution of the previous bias condition, or to the Newton corrections. The method is applied to solve PN-junctions and MOSFETs. The method provides an effective way to cover the changes of carrier distributions depending on bias conditions. The algorithm is simple and effective, and can be widely used.

Study of Heat Conduction in Corrugated Si Nanowires Using Raman mapping

Thermal properties of nanostructures have attracted growing interest, especially, in application in thermoelectrics. Due to size limitation in nanostructures, phonon mean free path (MFP) reduction takes place due to boundary scattering and, therefore, thermal conductivity decreases. However, recently, even stronger reduction of MFP was obtained in corrugated nanowires (NWs) at low temperatures [1]. Nearly one order reduction of thermal conductivity k of corrugated NWs compared to straight NW was demonstrated. The effect was attributed to multiple phonon scattering on corrugated surfaces. Further studies of this effect, especially, at room and higher temperatures are required for its mechanism clarification and practical application. In this work, we study heat conduction in a variety of corrugated Si NWs using Raman mapping. 5 and 10 micron long NWs were made from silicon-on-insulator (SOI) structure with ~1 micron thick buried oxide (BOX) layer using electron beam lithography with subsequent removal of BOX material under NWs in HF. As a result, sets of parallel suspended NWs connecting two SOI islands were fabricated. Figure 1 shows 55 nm thick corrugated NW with minimal width ~ 60 nm and maximal width ~ 150 nm. Raman measurement was done using Nanofinder 30 confocal Raman system (Tokyo Instruments Inc.) equipped with a scanner and a 561 nm wavelength laser. Lens with 100x magnification and 0.95 numerical aperture focusing laser light into ~350 nm spot was utilized. Figure 2 shows dependence of temperature increase T determined from temperature-induced NW Raman band downshift in laser-illuminated NW area on position along NW. Parabolic fitting of the dependence reveals a parameter proportional to k. Obtained data suggest that corrugations cause ~ 50% k reduction in the 300 – 400 K temperature range. This reduction is less pronounced than that reported in Ref. [1] for low temperatures but, nevertheless, our data suggest that NW corrugation is a promising technique for thermoelectrics fabrication. This work was partly supported by JST-ALCA project.