Koichi Fukuda

Monolithic Pixel Detector in a 0.15 μm SOI Technology

We describe a new pixel detector development project using a 0.15 μm fully-depleted CMOS SOI (silicon-on-insulator) technology. Additional processing steps for creating substrate implants and contacts to form sensor and electrode connections were developed for this SOI process. A diode test element group and several test chips have been fabricated and evaluated. The pixel detectors are successfully operated and first images are taken and sensibility to β-rays is confirmed. Back gate effects on the top circuits are observed and discussed.

SOI pixel developments in a 0.15μm technology

While the SOI (silicon-on-insulator) device concept is very old, commercialization of the technology is relatively new and growing rapidly in high-speed processor and low-power applications. Furthermore, features such as latch-up immunity, radiation hardness and high-temperature operation are very attractive in high energy and space applications. Once high-quality bonded SOI wafers became available in the late 90s, it opened up the possibility to get two different kinds of Si on a single wafer. This makes it possible to realize an ideal pixel detector; pairing a fully-depleted radiation sensor with CMOS circuitry in an industrial technology. In 2005 we started Si pixel R&D with OKI Electric Ind. Co., Ltd. which is the first market supplier of fully-depleted SOI products. We have developed processes for p+/n+ implants to the substrate and for making connections between the implants and circuits in the OKI 0.15mm FD-SOI CMOS process. We have preformed two multi project wafer (MPW) runs using this SOI process. We hosted the second MPW run and invited foreign universities and laboratories to join this MPW run in addition to Japanese universities and laboratories. Features of these SOI devices and experiences with SOI pixel development are presented.

Radiation resistance of SOI pixel devices fabricated with OKI 0.15μm FD-SOI technology

Silicon-on-insulator (SOI) technology is being investigated for monolithic pixel device fabrication. The SOI wafers by UNIBOND allow the silicon resistivity to be optimized separately for the electronics and detector parts. We have fabricated pixel detectors using fully depleted SOI (FD-SOI) technology provided by OKI Semiconductor Co. Ltd. The first pixel devices consisting of 32×32 pixels each with 20 μm square were irradiated with 60Co γ’s up to 0.60 MGy and with 70-MeV protons up to 1.3×1016 1-MeV n eq /cm2. The performance characterization was made on the electronics part and as a general detector from the response to RESET signals and to laser. The electronics operation was affected by radiation-induced charge accumulation in the oxide layers. Detailed evaluation using transistor test structures was separately carried out with covering a wider range of radiation level (0.12 kGy to 5.1 MGy) with 60Co γ’s.

Reduction techniques of the back gate effect in the SOI Pixel Detector

We have fabricated monolithic pixel sensors in 0.2 μm Silicon-On-Insulator (SOI) CMOS technology, consisting of a thick sensor layer and a thin circuit layer with an insulating buried-oxide, which has many advantages. However, it has been found that the applied electric field in the sensor layer also affects the transistor operation in the adjacent circuit layer. This limits the applicable sensor bias well below the full depletion voltage. To overcome this, we performed a TCAD simulation and added an additional p-well (buried pwell) in the SOI process. Designs and preliminary results are presented.

An interpolated flux scheme for cellular automaton device simulation

Cellular automaton (CA)-based device simulation is one of the most powerful tool to solve Boltzmann transport equation (BTE) of carriers in semiconductor devices. In comparison to the Monte Carlo (MC) method which suffers statistical noise problems, cell representation used in the CA method realizes noise free analysis of the carrier distribution function (DF) both in real and momentum space. However, CA requires more computer resources than MC in typical cases because cell sizes used for both real and momentum space are restricted to be small enough not to cause artificial diffusion (ADF). In this paper, a new scheme for calculation of flux among cells is proposed in which carrier distribution is interpolated between neighbor cells. The suppression of ADF is confirmed through comparisons to other simulation methods in homogeneous cases, an n/sup +/-p diode case and an n/sup +/-n-n/sup +/ structure case. Consistency with MC analysis is also demonstrated by analyzes of homogeneous cases and an n/sup +/-n-n/sup +/ case and also by a theoretical study. A speed up of at least two orders of magnitude can be obtained by introducing the new flux calculation whose accuracy is ensured with much less number of cells than conventional CA methods. Consequently, this CA method is drastically improved as a practical tool for semiconductor device modeling from the point of CPU time and accuracy.