Junichi Shibata
Panasonic
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Publication
Featured researches published by Junichi Shibata.
international interconnect technology conference | 2007
Takeshi Harada; Akira Ueki; Kazuo Tomita; K. Hashimoto; Junichi Shibata; H. Okamura; Kazunori Yoshikawa; T. Iseki; M. Higashi; S. Maejima; Kotaro Nomura; Kinya Goto; T. Shono; Seiji Muranaka; Naoki Torazawa; Shuji Hirao; M. Matsumoto; T. Sasaki; Susumu Matsumoto; S. Ogawa; Masahiko Fujisawa; A. Ishii; Masazumi Matsuura; Tetsuya Ueda
Dual damascene Cu interconnects with Keff below 2.0 have been demonstrated for the first time. Air gaps between Cu lines were formed with a low K SiOC film in a carefully designed manner. CoWP cap layers were introduced to protect the Cu lines and to eliminate a dielectric liner layer. In addition, AGE (Air Gap Exclusion) was applied to solve crucial problems related to the air gaps. Keff of 1.9 was obtained at 65 nm design rule, which surpassed by far ITRS target (2.5~2.8) for hp 45. It was also confirmed that leakage current between lines was suppressed by the formation of the air gaps.
international interconnect technology conference | 2010
Susumu Matsumoto; Takeshi Harada; Yasunori Morinaga; Daisuke Inagaki; Junichi Shibata; K. Tashiro; Tatsuya Kabe; A. Iwasaki; Shuji Hirao; Makoto Tsutsue; Kotaro Nomura; Kohei Seo; Toru Hinomura; Naoki Torazawa; Shigeru Suzuki; K. Kobayashi; Hayato Korogi; H. Okamura; Yusuke Kanda; T. Shigetoshi; M. Watanabe; K. Tomiyama; H. Shimizu; M. Matsumoto; T. Sasaki; T. Hamatani; K. Hagihara; Tetsuya Ueda
High performance 32nm-node interconnect with ELK (Extremely Low-k, k=3D2.4) has been demonstrated. To suppress process damage and enlarge the via-line space with a wide lithography process margin, robust ELK film with a metal hard mask (MHM) self-aligned via process has been developed. It has accomplished both ultimate low capacitance wirings and high TDDB reliability between Cu lines with vias. In addition, a novel technique of interface engineering between ELK and a liner layer has been developed to strengthen the tolerance against chip packaging. This has achieved highly reliable chip packaging. This complete process has a high manufacturability and it therefore offers a promising technology for the 32-nm node and beyond.
STRESS-INDUCED PHENOMENA IN METALLIZATION: Tenth International Workshop on#N#Stress-Induced Phenomena in Metallization | 2009
Tetsuya Ueda; Takeshi Harada; Akira Ueki; S. Kido; Kazuo Tomita; Yusuke Kanda; T. Sasaki; H. Tsuji; Takahisa Furuhashi; Tatsuya Kabe; Junichi Shibata; A. Iwasaki; J. Izumitani; Y. Kawano; Susumu Matsumoto
45 nm‐node Cu interconnects with air gaps were studied to confirm the feasibility to the next node (32 nm) and beyond. The air‐gap formation technology that we proposed was characterized by “air‐gap exclusion” (AGE), which selectively excluded the air gaps from undesired regions such as wide spaces between lines and peripheries of vias. A high‐Young’s‐modulus SiOC (HM‐SiOC) with k value of 3.0 was used to form the air gaps. However, effective dielectric constant (Keff) as low as 2.3, which surpassed ITRS requirement for hp45 by far, was obtained. Mechanical characteristics of the Cu interconnects structure with the air gaps were studied systematically. Effective Young’s elastic modulus was measured by a nano‐indention method. The measurements show that it changes little with air‐gap density. A nano‐scratch test revealed that dominant fracture mode of the Cu interconnects structure with air gaps was not collapse of the air gaps but delaminations between the dielectrics. In addition, above phenomena are exp...
international interconnect technology conference | 2011
Naoki Torazawa; Toru Hinomura; Takeshi Harada; Tatsuya Kabe; Daisuke Inagaki; Yasunori Morinaga; Junichi Shibata; Takushi Shigetoshi; Shunsuke Hazue; Dai Motojima; Susumu Matsumoto; Takenobu Kishida
One of the most challenging issues in the metal hard mask (MHM) process is controlling the residual stress in TiN mask. This becomes more important as the feature sizes of trenches and vias continue to shrink and the low k-value dielectrics are introduced to Cu interconnect. It is found that the deformation of trenches due to the residual stress in TiN results in Cu voids forming. To overcome this problem, the correlation between the residual stress and the film property of TiN has been investigated. The residual stress in TiN is found to strongly correlate with both the grain size and the crystal structure of TiN, and low residual stress in TiN is accomplished by suppressing the grain growth of TiN. By applying TiN that has a quite fine needle-like structure, the trench deformation can be suppressed and thus the gap filling is perfectly achieved. The MHM process using TiN film that has a needle-like structure is a promising technology for 32-nm node Cu interconnect and beyond.
Archive | 2011
Kazuo Tagawa; Yuji Shimomura; Ken Sawada; Katsuya Takigawa; Toshio Yoshida; Shinichi Mitsumoto; Eiji Akiyama; Junichi Shibata; Satoshi Suda; Hideo Yokota; Masahiro Hata; Hiroyuki Hoshino; Hajime Nakao; Shozaburo Konishi
Archive | 2010
Junichi Shibata; Tadaaki Motoyama; Kazuhiko Endou
Archive | 2011
Kazuo Tagawa; Yuji Shimomura; Ken Sawada; Katsuya Takigawa; Toshio Yoshida; Shinichi Mitsumoto; Eiji Akiyama; Junichi Shibata; Satoshi Suda; Hideo Yokota; Masahiro Hata; Hiroyuki Hoshino; Hajime Nakao; Shozaburo Konishi
Archive | 2011
Kazuo Tagawa; Yuji Shimomura; Ken Sawada; Katsuya Takigawa; Toshio Yoshida; Shinichi Mitsumoto; Eiji Akiyama; Junichi Shibata; Satoshi Suda; Hideo Yokota; Masahiro Hata; Hiroyuki Hoshino; Hajime Nakao; Shozaburo Konishi
Archive | 2010
Junichi Shibata; Norio Sembongi; Masanori Ibi; Satoshi Suda
Archive | 2010
Hideyuki Itou; Yasuhiro Hibino; Junichi Shibata