Junji Kitamichi

Evolution of Software-Defined Sensor Networks

After a decade of extensive research on application-specific wireless sensor networks (WSNs), the recent development of information and communication technologies make it practical to realize new WSNs paradigm known as software-defined sensor networks (SDSNs). SDSNs are able to adapt to various application requirements and to fully explore the communication, computation and sensing resources of WSNs. Sensor nodes in SDSNs can be dynamically reprogrammed for different sensing tasks via the over-the-air-programming technique. In this paper, we introduce the concept of SDSNs and outline several pioneering related work and enabling technologies for the realization of SDSNs.

A software defined wireless sensor network

We propose a software-defined wireless sensor network system whose behavior can be redefined even after deployment by the injection of sensor node roles by means of wireless network communications. Two main technologies are used to develop this system, role generation and delivery mechanism, and a reconfigurable wireless sensor network with many reconfigurable sensor nodes. In the role generation and delivery mechanism, a scenario compiler generates roles for sensor nodes based on a user-defined scenario description and then delivers the roles to appropriate nodes. We also propose a reconfigurable sensor node composed of an ultra-low power field programmable gate array (FPGA) and a microcontroller unit (MCU) for altering network behavior. By assigning heavy tasks such as sensor and data processing to the FPGA, overloading of the MCU can be avoided. Using wireless communication, both configuration data for the FPGA and programs to run on the MCU can be injected as roles from outside of the sensor node, enabling easy alteration of sensor node functionality depending on situation and/or application. After introduction of a system overview, a prototype system is described and some experimental results are discussed.

Dynamic Module Library for System Level Modeling and Simulation of Dynamically Reconfigurable Systems

In this paper, we propose a library for the system level modeling and simulation of the system which includes Dynamically Reconfigurable Architectures (DRAs). The proposed library is an extended SystemC library. Using the proposed library, the designer can model the system specifications including modules for the dynamic generation and elimination and ports and channels for the dynamic connection and dispatch between them, that are needed in the design of general-purpose dynamically reconfigurable systems at the system design level. In addition, we evaluate the proposed library by the modeling and simulation of sample circuits, such as partially DRA and multi context DRA. Using the proposed library, we can model the system specifications naturally, and as much the same amount as a description, such as one using multiplexers and demultiplexers, which is a modeling formula for describing multi-context DRA. Under some conditions, higher-speed simulation is possible using the proposed library.

A gradual neural network approach for FPGA segmented channel routing problems

A novel neural network approach called gradual neural network (GNN) is presented for segmented channel routing in field programmable gate arrays (FPGAs). FPGAs contain predefined segmented channels for net routing, where adjacent segments in a track can be interconnected through programmable switches for longer segments. The goal of the FPGA segmented channel routing problem, known to be NP-complete, is to find a conflict-free net routing with the minimum routing cost. The GNN for the N-net-M-track problem consists of a neural network of NxM binary neurons and a gradual expansion scheme. The neural network satisfies the constraints of the problem, while the gradual expansion scheme seeks the cost minimization by gradually increasing activated neurons. The energy function and the motion equation are newly defined with heuristic methods. The performance is verified through solving 30 instances, where GNN finds better solutions than existing algorithms within a constant number of iteration steps.

A gradual neural-network algorithm for jointly time-slot/code assignment problems in packet radio networks

A gradual neural network (GNN) algorithm is presented for the jointly time-slot/code assignment problem (JTCAP) in a packet radio network in this paper. The goal of this newly defined problem is to find a simultaneous assignment of a time-slot and a code to each communication link, whereas time-slots and codes have been independently assigned in existing algorithms. A time/code division multiple access protocol is adopted for conflict-free communications, where packets are transmitted in repetition of fixed-length time-slots with specific codes. GNN seeks the time-slot/code assignment with the minimum number of time-slots subject to two constraints: 1) the number of codes must not exceed its upper limit and 2) any couple of links within conflict distance must not be assigned to the same time-slot/code pair. The restricted problem for only one code is known to be NP-complete. The performance of GNN is verified through solving 3000 instances with 100-500 nodes and 100-1000 links. The comparison with the lower bound and a greedy algorithm shows the superiority of GNN in terms of the solution quality with the comparable computation time.

Automatic Correctness Proof of the Implementation of Synchronous Sequential Circuits Using an Algebraic Approach

In this paper, we propose a technique for proving the correctness of the implementations of synchronous sequential circuits automatically, where the specifications of synchronous sequential circuits are described in an algebraic language ASL, which we have designed, and the specifications are described in a restricted style. For a given abstract levels specification, we refine the specification into a synchronous sequential circuit step by step in our framework, and prove the correctness of the refinement at each design step. Using our hardware design support system, to prove the correctness of a design step, we have only to give the system some invariant assertions and theorems for primitive functions. Once they are given, the system automatically generates the logical expressions from the invariant assertions and so on, whose truth guarantees the correctness of the design step, and tries to prove those truth using a decision procedure for the prenex normal form Presburger sentences bounded by only universal quantifiers. Using the system, we have proved the correctness of the implementation of a GCD circuit, the Tamarack microprocessor, a sorting circuit and so on, in a few days. The system has determined the truth of each logical expression within a minute.

A master-slave adaptive load-distribution processor model on PCA

In this paper, we propose a new load-distribution processor model that adapts hardware resources optimally and autonomously to target applications on dynamical reconfiguration devices. In the procedure of load-distribution, the processor detects the load of task-processing by itself and changes the kinds and number of resources optimally. We adopt the master-slave model, which consists of a management unit (master) and two or more processing units (slaves). The former detects overload and distributes tasks and the latter execute task-processing. One of the features of this model is that it is possible to change the number of processing units without reconfiguring the management units structure. Moreover, in order to use this load-distribution system efficiently, we propose a reordering unit that buffers data from processing units and outputs rearranged data. In this paper, we describe the requirements and organization of a management unit and processing units. Next, we implement the proposed model on real chips of PCA, a dynamical reconfiguration device, and measure the overheads of processing and reconfiguration. Finally, we evaluate the proposed model based on the experimental results. From the experiments, we show that our proposed model can reduce a designers efforts to estimate the amount of hardware resources according to applications in advance.

A conformance testing method for communication protocols modeled as concurrent DFSMs. Treatment of non-observable non-determinism

According to the progress of high-speed networks, many communication protocols are specified as concurrent systems. Such systems can be modeled as concurrent deterministic FSMs (DFSMs). In those protocols, a common input may be taken by some of concurrent DFSMs competitively. In such a case, the global behaviour becomes non-deterministic in general. Conformance testing is typically a black-box testing, i.e. it is based on its specification. Formal methods for deriving conformance test cases are widely recognized as being capable of producing tests with high fault coverage. We propose a conformance testing method based on GWp-method for a sub-class of non-observable non-deterministic FSMs (NFSMs). In this class, the global behaviour of many protocols modeled as concurrent DFSMs can be specified. The proposed method can be used not only for testing NFSMs directly but also for testing concurrent DFSMs whose global behaviour becomes non-observable non-deterministic.

Demand-Addressable Sensor Network: Toward Large-Scale Active Information Acquisition

A new type of sensor network called the demand-addressable sensor network (DASN) is proposed in this paper. The DASN actively acquires the desired information by addressing user demands and delivers the information to appropriate destinations. This is in contrast to the conventional sensor networks that simply send sensed data to users. The DASN is useful for finding the desired information in a short duration of time from a large amount of sensed data generated by a large-scale sensor network. The DASN is constructed with a demand-addressable network that integrates many on-demand reconfigurable wireless sensor networks (ODRWSN) and other existing information and communications technology systems or services, such as Google Maps and Twitter. In addition to the demand-addressing mechanism, the demand-addressable network has an in-network data combining or mashup mechanism. The mashed up data are displayed on the user terminal using an ordinary Web browser without any requirement to install a dedicated application program. The functions of the ODRWSN can be dynamically customized by injecting roles specified by the user. Thus, the user can actively get the desired information by customizing the sensor network function. The main application of the DASN is wide-area disaster site monitoring, for which the DASN features outlined above are suitable. In this paper, the concept underlying the DASN, its architecture and implementation, and experimental results are presented.

On-demand Customizable Wireless Sensor Network☆

Abstract In this paper, we propose a wireless sensor network (WSN) whose behavior can be dynamically customized by injecting programs or roles specified by the user. To enable easy specification of the roles, a role-generation mechanism is also proposed. To realize the WSN, we introduce a reconfigurable wireless sensor node that has an ultra-low-power field-programmable gate array (FPGA) as well as a low-power microcontroller unit (MCU). By injecting several different roles into the sensor nodes, we confirmed that the behavior of the WSN can be changed on demand.