Jupyo Hong

Design optimization on the heat transfer and mechanical reliability of High Brightness Light Emitting Diodes (HBLED) package

In this study, high brightness LED package is considered. Steady state heat transfer process analysis is firstly carried out using 3-D finite element method. Temperature distribution and thermal resistance of the package are then determined. The FEM results are evaluated by thermal resistance measurement on the package by T3STer system. In addition design study on the thermal performance of the packaging structure is also performed. The analysis results show that die attachment (solder material) plays the most important role in the thermal resistance of LED package. Thermal resistance of the package is mainly caused by the interfacial thermal resistances. It can be found out that AI2O3 isolation ring increases the thermal resistance of the package and pure Aluminum substrate achieves a better performance in the respect of thermal behavior of packaging designs. Mechanical reliability analysis has also been carried out. Failure of the package occurs in the anodized AI2O3 isolation ring during die bonding process due to the material defects of AI2O3 in the manufacturing process. 3D mechanical FEM is used to figure out the failure mechanism. Design optimization on the packaging structure is also performed to improve the mechanical reliability. A few new structure designs are proposed, analyzed and compared. Design with the best reliability among the candidates is chosen and the corresponding manufacturing processes are proposed.

Reliability evaluation and structure design optimization of Wafer Level Chip Scale Packaging (WLCSP)

In this study a WLCSP structure in microelectronic application is considered. In the current development of WLCSP solder post is used to bridge the die and solder bump to release part of the stress concentration caused by mismatch of Thermal Expansion Coefficient (CTE). Thermal cycle reliability analysis on solder joints with 3D finite element simulation is firstly carried out. The stress/creep strain distribution and evolution are analyzed and the fatigue lives of solder joints are estimated. Finite element model is also verified and the fatigue property of currently used solder is determined with JEDEC thermal cycle reliability test. Structure design optimization is thereafter performed to improve the reliability of WLCSP. Parametric studies on the geometry structures are carried out, such as die thickness, solder post height and solder bump diameter, etc. The results show that solder post does great help to improve the solder bumpspsila reliability, the height of which plays an important role in controlling the fatigue life of the package. Higher post helps to release the stress concentration and therefore extend the fatigue life of solder bumps. In addition, die thickness plays the most important role in affecting fatigue life of solder joints. The thinner the die, the better the reliability of WLCSP is. Other parameters, such as the diameter of the solder bump, only have tiny effect on the solder joints reliability of WLCSP.

Parametric design study for minimized warpage of WL-CSP

WL-CSP (wafer level - chip scale package) has many advantages such as low cost, easy fabrication and ultimate miniature size, even though solder joint reliability (SJR) of conventional WL-CSP is critical weak point of the technology. Therefore, many advanced structure of WL-CSP has been developed to improve SJR such as using Cu post covered with encapsulation material. One of advanced WL-CSP is using encapsulated e double solder bump structure that the first bump is covered with epoxy molding compound (EMC) to protect. Fig.1 shows both conventional and encapsulated double bump type WL-CSP structure. However, the warpage of this advanced WL-CSP is much higher than conventional one due to CTE mismatch between silicon wafer and EMC material, which generates failure such as wafer crack or manufacturing difficulty such as process handling. In this paper, WL-CSP which has 120 mum EMC thickness on 6 inch wafer has been developed for advanced high I/O density applications. The warpage of WL-CSP after EMC curing process is considered. 3D thermo-mechanical FEM simulation is carried out the warpage distribution after curing process. The results also present the main factor in materials to affect the WL-CSP warpage. The lower Youngpsilas modulus and EMC CTE for encapsulation achieves less warpage. Furthermore, we studied some structures to reduce the warpage of WLCSP such as adding other material on backside of wafer and using patterned EMC. Both structures can make the WL-CSP structure balanced.

Warpage control of wireless LAN SiP during manufacturing process

In this study, the warpage of WLAN strip after reflow process, which contains 7times5 WLAN modules, is considered. 3D thermo-mechanical FEM simulation is carried out to find out the warpage distribution and maximum warpage after reflow process. Experimental investigation on the warpage measurement of the package is also performed to verify the simulation results. Furthermore, some new designs on the manufacturing of the module strip, such as reducing the density of module or cutting grooves on the PCB, adding extra pins on the carrier, are proposed and compared with the currently used one. The results show that pin carrier is an effective way to reduce the warpage. The more pins on the carrier, the more efficient in reducing the warpage. Decreasing the unit density on the PCB or cutting grooves in the PCB are also ways to reduce the warpage. The less units on a single PCB sheet, the smaller the warpage. The most effective method to reduce strip warpage is to add a central pin on the PCB which can help control the maximum warpage to be within 50 mum.

Study of a Wafer Level Package (WLP) for Surface Acoustic Wave (SAW) Filter

In this paper, a numerical study based on the three-dimensional thermo-mechanical finite element method (FEM) has been conducted to analyze the reliability of SAW filter WLP. The 3D FEM model was firstly evaluated based on a benchmark analysis. The validated model is then applied to perform parametric studies on the effects of package geometry, material properties and the processing conditions on the reliability of the package. The stresses and warpages of the package have been analyzed and the critical failure zones have been pointed out. The results show that the CTE of materials play a key role in the reliability of WLP. The maximum stresses and warpages are very sensitive to the CTE of the materials, especially via, the material of which is copper. In addition, the optimal thermo-mechanical properties of materials have been selected to achieve the minimum thermal stress during wafer bonding process based on the parametric studies.

Design Optimization of a Wafer Level Package for Surface Acoustic Wave Filters

In this paper, wafer level packaging of a surface acoustic wave (SAW) filter is considered. Numerical studies based on a three-dimensional finite element method (FEM) have been conducted in order to evaluate the reliability of a wafer level SAW package. The effects of package geometric parameters, such as the diameter of via hole and wafer thickness, on the reliability of the wafer level SAW package have been studied. The results show that the diameter of via hole for interconnection plays a key role in the reliability of the SAW package because the CTE mismatch between the filling materials of via holes (copper) and surrounding cap wafer martial (LiTiO3) is the highest among the material pairs in the package. Such CTE mismatch leads to the maximum stresses and warpages. The optimal thermo-mechanical properties of packaging materials have been proposed to achieve the minimum thermal stress during reflow process. Moreover, numerical results have also been compared with the experimental ones to validate the FEM model.Copyright

Heat Transfer Analysis and Design Optimization of ALOX High Brightness Light Emitting Diode Package

High Brightness (HB) Light emitting diode (LED) technology is becoming the choice for many lighting applications. However, one potential problem with LED based lighting systems is the thermal issue during service, which has restricted LED in the application of mini-devices. In this study, thermal performance of Al2 O3 (ALOX) based HBLED package is considered. Steady state heat transfer analysis is carried out using 3-D finite element method (FEM). A new algorithm has firstly been developed, which combines FEM analysis and thermal transient experimental investigation, to determine the interfacial thermal properties of the package. Then the interfacial thermal properties are applied in the FEM model for heat transfer analysis. Temperature distribution and heat flux analysis are calculated and thermal resistance of the package is determined based on the FEM simulation. The results show that die attachment (solder material) plays the most important role in the thermal resistance of the ALOX package, i.e., it takes about 80% of the total thermal resistance. In addition, thermal resistance of the package is mainly caused by the interfacial thermal resistances, the behavior of which depends strongly on manufacturing processes. The parametric study shows that Al2 O3 isolation ring increases the thermal resistance of the package because it creates an interface inside the aluminum substrate. Pure Aluminum substrate achieves a better performance in the respect of thermal behavior of packaging designs.Copyright

Effect of Underfilling Materials and Processes on the Reliability of System in Package

During the manufacturing process of the system-in-package, it has become susceptible to defects and internal residual stresses when dies, components, electric functionality and geometric complexity have increased. The mismatch of thermal expansion coefficient (CTE) among packaging materials and devices may lead to various failure modes during manufacturing processes, such as die broken, solder crack, substrate interface delamination. In this paper, the effect of underfill on the reliability of a system-in-package has been studied. A Bluetooth package is considered. The dimension of the package is 4.84 (L) × 6.15 (W) × 1.32 (H) mm. It contains an IC chip and several passive components such as crystals and filters. The substrate is NSMD type. Three underfill materials are considered. Materials were selected based on the numerical simulation. The causes of void formation during the underfill process have been investigated. In addition, the adhesion test of die passive material and PCB solder register was performed.© 2007 ASME