Seogmoon Choi

Large Displacement Polymer Bimorph Actuator for Out-of-Plane Motion

A new thermal bimorph actuator for large out-of-plane displacement is designed, fabricated and tested. The deflecting beam is composed of polyimide, heater, and polyvinyl difluorides with tetrafluoroethylene (PVDF-TrFE). The large difference of coefficient of thermal expansion (CTE) of two polymer layers (polyimide and PVDF-TrFE) can generate a significant deflection with relatively small temperature rise. Compared to the most conventional micro actuators based on MEMS (micro-electro mechanical system) technology, a large displacement, over 1 mm at 20 mW, could be achieved. Additionally, we can achieve response time of 14.6 ms, resonance frequency of 12 Hz, and reliability ability of 10 5 cycles. The proposed actuator can find applications where a large vertical displacement is needed while maintaining compact overall device size, such as a micro zooming lens, micro mirror, micro valve and optical application.

Design optimization on the heat transfer and mechanical reliability of High Brightness Light Emitting Diodes (HBLED) package

In this study, high brightness LED package is considered. Steady state heat transfer process analysis is firstly carried out using 3-D finite element method. Temperature distribution and thermal resistance of the package are then determined. The FEM results are evaluated by thermal resistance measurement on the package by T3STer system. In addition design study on the thermal performance of the packaging structure is also performed. The analysis results show that die attachment (solder material) plays the most important role in the thermal resistance of LED package. Thermal resistance of the package is mainly caused by the interfacial thermal resistances. It can be found out that AI2O3 isolation ring increases the thermal resistance of the package and pure Aluminum substrate achieves a better performance in the respect of thermal behavior of packaging designs. Mechanical reliability analysis has also been carried out. Failure of the package occurs in the anodized AI2O3 isolation ring during die bonding process due to the material defects of AI2O3 in the manufacturing process. 3D mechanical FEM is used to figure out the failure mechanism. Design optimization on the packaging structure is also performed to improve the mechanical reliability. A few new structure designs are proposed, analyzed and compared. Design with the best reliability among the candidates is chosen and the corresponding manufacturing processes are proposed.

LED packaging using high sag rectangular microlens array

A novel rectangular shape microlens array having high sag for solid-state lighting is presented. Suggested microlens array which have high sag is realized using photoresist reflow and replication technique. Applying to the light-emitting-diode (LED) packaging, the rectangular shape of proposed microlens can maximize the fill factor of silicon based LED packaging and minimize the optical loss through the reduction of unnecessary reflection at the same time. Microlens, which has high sag, over 375 μm and large diameter, over 3 mm can enormously enhance output optical extraction efficiency. Moreover wafer level packaging technology is used to improve the aligning accuracy and mass production of LED packaging. This wafer level microlens array can be directly fabricated on LED packaging using replication method. It has many advantages in optical properties, low cost, high aligning accuracy, and mass production. Therefore wafer level LED packaging method adopts high sag rectangular microlens array demonstrates only improved optical performance but also mass production capability.

Studies on the Thermal Cycling Reliability of BGA System-in-Package (SiP) With an Embedded Die

Nowadays, major trends in the design of electronic products are toward multifunction and miniaturization. To meet these trends, system-in-package (SiP) has been adapted as one of the core packaging technologies for many product applications. Among the various types of SiPs, SiP with embedded dies has become important due to the smaller size achieved through embedded dies and better electrical performance by the shorter interconnection length. However, reliability data of the SiP with embedded dies have not been reported yet. Therefore, it is necessary to investigate the reliability of the SiPs with embedded dies and the effect of the embedded die on the SiP reliability. Of the several reliability tests, a detailed thermal cycling test (T/C test) was performed on board-level packaged samples. A finite element method (FEM) simulation was also performed to find out the stress and strain distribution of ball grid array (BGA) solder positions and to predict the potential failure sites under the T/C test. Through this paper, it was found that the failure position of the BGA changed from the corner solder ball position of the conventional BGA package, where the largest distance from neutral point was, to the inner BGA solder ball positions, where the edge of embedded die was located, due to the complicated structure of embedded die SiPs. Furthermore, FEM results showed that the inner site of the BGA is more vulnerable than the corner BGAs. This was well matched with experimental results.

Issues in junction-to-case thermal characterization of power packages with large surface area

There are several ways to define the junction-to-case thermal resistance; however, it is rather challenging to characterize the heat-flow in a package by a single number in an accurate and reproducible way. For many power package families such as TO-type packages the thermal transient testing and the so-called dual interface method can give reliable results. The diverging point of structure functions from dual thermal transients gives a good picture of the material interfaces in such structures. However, the location and nature of the diverging point strongly depends on the shape and direction of the heat-spreading. If the package area is much larger than the dissipating chip the shape of the heat-flow changes when using different interfaces. This causes structure functions corresponding to the two setups deviate much before reaching the case surface. In this paper the origin of this phenomenon is investigated. Measurement and simulation results are compared on different large IGBT modules with several modifications in their structure enabling a detailed analysis of the heat-flow path. A comparison is given between heating only a small fraction of a large module and heating all chips. Some samples went through thermal cycling reliability tests which resulted in cracks below the chips. The effect of the reduced die-attach area is visualized with the help of structure functions.

Reliability evaluation and structure design optimization of Wafer Level Chip Scale Packaging (WLCSP)

In this study a WLCSP structure in microelectronic application is considered. In the current development of WLCSP solder post is used to bridge the die and solder bump to release part of the stress concentration caused by mismatch of Thermal Expansion Coefficient (CTE). Thermal cycle reliability analysis on solder joints with 3D finite element simulation is firstly carried out. The stress/creep strain distribution and evolution are analyzed and the fatigue lives of solder joints are estimated. Finite element model is also verified and the fatigue property of currently used solder is determined with JEDEC thermal cycle reliability test. Structure design optimization is thereafter performed to improve the reliability of WLCSP. Parametric studies on the geometry structures are carried out, such as die thickness, solder post height and solder bump diameter, etc. The results show that solder post does great help to improve the solder bumpspsila reliability, the height of which plays an important role in controlling the fatigue life of the package. Higher post helps to release the stress concentration and therefore extend the fatigue life of solder bumps. In addition, die thickness plays the most important role in affecting fatigue life of solder joints. The thinner the die, the better the reliability of WLCSP is. Other parameters, such as the diameter of the solder bump, only have tiny effect on the solder joints reliability of WLCSP.

Effects of Packaging Materials on the Reliability of System in Package

System in package (SiP) has the ability to integrate other components, such as passive component and antenna, into a single package to realize complete system functions. However, there are many electrical and mechanical reliability issues including the reliability issue for embedded structures. A mismatch of thermal coefficients of expansion among packaging materials and devices can lead to warping or delamination in the package. In tins study, the effect of material properties of underfill and EMC, such as Youngs modulus and CTE are investigated through FEM simulation. In the FEM analysis, the warpage of the package, the maximum principle stress in the die and the maximum shear stress on the interface between the substrate, undefill and EMCs surface are considered. Experimental investigation on the warpage measurement of the package is carried out to verify the simulation results. In addition, some geometry parameters, such as the underfills profile and EMC thickness, are also considered as the influencing parameters for the reliability of the package. Process optimization study. i.e.. replacing underfill with EMC is also carried out to improve the manufacturing process. The results show that the reliability of the system in package is closely related to the material properties and the geometry structures of underfill and EMC. The replacement of underfill with EMC improves the reliability performance of the package significantly. Results of this study provide a good guidance for the structure/process design and material selection when developing a SiP module.

Parametric design study for minimized warpage of WL-CSP

WL-CSP (wafer level - chip scale package) has many advantages such as low cost, easy fabrication and ultimate miniature size, even though solder joint reliability (SJR) of conventional WL-CSP is critical weak point of the technology. Therefore, many advanced structure of WL-CSP has been developed to improve SJR such as using Cu post covered with encapsulation material. One of advanced WL-CSP is using encapsulated e double solder bump structure that the first bump is covered with epoxy molding compound (EMC) to protect. Fig.1 shows both conventional and encapsulated double bump type WL-CSP structure. However, the warpage of this advanced WL-CSP is much higher than conventional one due to CTE mismatch between silicon wafer and EMC material, which generates failure such as wafer crack or manufacturing difficulty such as process handling. In this paper, WL-CSP which has 120 mum EMC thickness on 6 inch wafer has been developed for advanced high I/O density applications. The warpage of WL-CSP after EMC curing process is considered. 3D thermo-mechanical FEM simulation is carried out the warpage distribution after curing process. The results also present the main factor in materials to affect the WL-CSP warpage. The lower Youngpsilas modulus and EMC CTE for encapsulation achieves less warpage. Furthermore, we studied some structures to reduce the warpage of WLCSP such as adding other material on backside of wafer and using patterned EMC. Both structures can make the WL-CSP structure balanced.

Chip-On-ACB (Anodized Circuit Board) Package for High Power Light-Emitting Diode

A new light-emitting diode (LED) package module based on anodized circuit board (ACB) is developed in this study. ACB represents the selectively anodized aluminum board, in which the aluminum oxide layer, formed by anodizing process, serves as a dielectric layer and the electric signal lines are formed on it. LED chips can be directly attached to the metal pads on the aluminum core of ACB, which acts as p-electrode and at the same time easily spreads out the heat generated from the chips. The use of ACB in LED packaging has the benefit that ACB provides an excellent heat dissipation path from junction to board. This characteristic cannot be obtained from metal-core printed circuit board (MC-PCB), because it inevitably has a dielectric layer for electrical insulation of signal lines from metal base, which acts as a blocking layer in the heat path. By using the thermal transient method, the thermal resistance of the LED package (from junction to board) is measured to be about 4 °C/W. Also, we have performed...

Warpage control of wireless LAN SiP during manufacturing process

In this study, the warpage of WLAN strip after reflow process, which contains 7times5 WLAN modules, is considered. 3D thermo-mechanical FEM simulation is carried out to find out the warpage distribution and maximum warpage after reflow process. Experimental investigation on the warpage measurement of the package is also performed to verify the simulation results. Furthermore, some new designs on the manufacturing of the module strip, such as reducing the density of module or cutting grooves on the PCB, adding extra pins on the carrier, are proposed and compared with the currently used one. The results show that pin carrier is an effective way to reduce the warpage. The more pins on the carrier, the more efficient in reducing the warpage. Decreasing the unit density on the PCB or cutting grooves in the PCB are also ways to reduce the warpage. The less units on a single PCB sheet, the smaller the warpage. The most effective method to reduce strip warpage is to add a central pin on the PCB which can help control the maximum warpage to be within 50 mum.