Jürgen T. Rickes

Preisach model for the simulation of ferroelectric capacitors

The emerging ferroelectric technology needs a reliable model for the simulation of the ferroelectric capacitors. This model would play a crucial role in designing new ferroelectric nonvolatile memories. As a main requirement, such a model must allow the calculation of the polarization variations for an arbitrary voltage applied to the ferroelectric. However, in spite of the large efforts made in modeling, most of the existing solutions fail to satisfy the above requirement or lack a minimal physical background. To address these problems, we developed a model based on a ferroelectric interpretation of the Preisach theory of hysteresis. In this articles, we try to elucidate how this theory, initially developed for ferromagnetic particles, can be adapted to the ferroelectric materials, despite the many differences between the two. Because the Preisach theory assumes a distribution of the coercitive voltages, we try to clarify its physical meaning in the case of the ferroelectric materials and propose a methodology to determine this distribution experimentally. To facilitate the implementation of the model, the experimental results are then fitted by an analytic function and the whole bidimensional distribution is calculated using a linear approximation. To evaluate the validity of the model, we performed simulations using the Spectre® circuit simulator and the results are in very good agreement with the measurements for the saturated hysteresis loops. The differences existing for the partial loops are mainly due to the linear approximation used for the Preisach distribution. This model can be successfully used for the design of the real memories.

Demonstration of a 4 Mb, high density ferroelectric memory embedded within a 130 nm, 5 LM Cu/FSG logic process

We demonstrate the bit functionality of a low-voltage, embedded ferroelectric random-access memory constructed using a 130 nm gate and five-level Cu/FSG interconnect process. By inserting the two additional masks required for the eFRAM module into this logic flow, we have co-integrated ferroelectric memory and SRAM on a single wafer.

A Novel Sense-Amplifier and Plate-Line Architecture for Ferroelectric Memories

We present a novel sense-amplifier for FeRAM that is about 2.5 times faster than the conventional sense-amplifier. In addition, it has truly independent sense and write-back capability and resolves the well-known bit-line capacitance imbalance issues. Moreover, thanks to separate write-back, data can be started on its path to the chips data output buffer, irrespective of the time required to accomplish the write-back. Furthermore, a new plate-line architecture that reduces the load per plate-line compared to conventional global plate-line schemes and employs full CMOS drivers is presented. A boosted gate voltage is not required. Therefore, it is ideal for ultra-low voltage operation. For a ferroelectric memory in 0.13 w m CMOS technology that employs the new sense amplifier and the new plate-line architecture a simulated read/write cycle time of <20 ns at 1.5 volt was observed.

Circuit design issues affecting present and future deep sub-micron ferroelectric random-access memories

Abstract The basic architecture of ferroelectric memories (FeRAMs) is known to be very similar to that of DRAM. Consequently, many design issues for FeRAM are already known from DRAM and have been solved by applying prior DRAM solutions. However, there are also a number of issues that are unique to FeRAM. Often these issues become critical design problems that require innovative circuit-level solutions[1]. This paper discusses some of the most relevant issues affecting present and future deep sub-micron FeRAMs. In addition, new problems that have to be solved for future FeRAMs are presented.

Comparison between standard and chain-type FRAM architectures

Abstract A standard 1T/1C and chain-type ferroelectric memory architecture are presented. The standard memory cell consists of a transistor connected in series to a ferroelectric capacitor while the chain-type cell connects these elements in parallel. Based on the different memory cells, two different arrays have been designed, simulated, and integrated on a single test chip in a 0.35μm process (not presented in this work). They are compared in regard to area, performance, and reliability. It is shown that chain FRAM has the potential to be superior to standard FRAM concerning area because of its innovative cell configuration which reduces the average number of lines per row from two to almost one and therefore removing the connectivity drawback required for bipolar polarization of ferroelectric materials compared to unipolar dielectric polarization. However, this obviously comes at the cost of limited performance and increased design complexity.