Ralph H. Lanham

Demonstration of a 4 Mb, high density ferroelectric memory embedded within a 130 nm, 5 LM Cu/FSG logic process

We demonstrate the bit functionality of a low-voltage, embedded ferroelectric random-access memory constructed using a 130 nm gate and five-level Cu/FSG interconnect process. By inserting the two additional masks required for the eFRAM module into this logic flow, we have co-integrated ferroelectric memory and SRAM on a single wafer.

A Novel Sense-Amplifier and Plate-Line Architecture for Ferroelectric Memories

We present a novel sense-amplifier for FeRAM that is about 2.5 times faster than the conventional sense-amplifier. In addition, it has truly independent sense and write-back capability and resolves the well-known bit-line capacitance imbalance issues. Moreover, thanks to separate write-back, data can be started on its path to the chips data output buffer, irrespective of the time required to accomplish the write-back. Furthermore, a new plate-line architecture that reduces the load per plate-line compared to conventional global plate-line schemes and employs full CMOS drivers is presented. A boosted gate voltage is not required. Therefore, it is ideal for ultra-low voltage operation. For a ferroelectric memory in 0.13 w m CMOS technology that employs the new sense amplifier and the new plate-line architecture a simulated read/write cycle time of <20 ns at 1.5 volt was observed.

Circuit design issues affecting present and future deep sub-micron ferroelectric random-access memories

Abstract The basic architecture of ferroelectric memories (FeRAMs) is known to be very similar to that of DRAM. Consequently, many design issues for FeRAM are already known from DRAM and have been solved by applying prior DRAM solutions. However, there are also a number of issues that are unique to FeRAM. Often these issues become critical design problems that require innovative circuit-level solutions[1]. This paper discusses some of the most relevant issues affecting present and future deep sub-micron FeRAMs. In addition, new problems that have to be solved for future FeRAMs are presented.