Justin L. Tripp

Trident: From High-Level Language to Hardware Circuitry

Unlocking the potential of field-programmable gate arrays requires compilers that translate algorithmic high-level language code into hardware circuits. The Trident open source compiler translates C code to a hardware circuit description, providing designers with extreme flexibility in prototyping reconfigurable supercomputers

Trident: an FPGA compiler framework for floating-point algorithms

Trident is a compiler for floating point algorithms written in C, producing circuits in reconfigurable logic that exploit the parallelism available in the input description. Trident automatically extracts parallelism and pipelines loop bodies using conventional compiler optimizations and scheduling techniques. Trident also provides an open framework for experimentation, analysis, and optimization of floating point algorithms on FPGAs and the flexibility to easily integrate custom floating point libraries.

Metropolitan road traffic simulation on FPGAs

This work demonstrates that road traffic simulation of entire metropolitan areas is possible with reconfigurable supercomputing that combines 64-bit microprocessors and FPGAs in a high bandwidth, low latency interconnect. Previously, traffic simulation on FPGAs was limited to very-short road segments or required a very large number of FPGAs. Our data streaming approach overcomes scaling issues associated with direct implementations and still allows for high-level parallelism by dividing the data sets between hardware and software across the reconfigurable supercomputer. Using one FPGA on the Cray XD1 supercomputer, we are able to achieve a 34.4/spl times/ speed up over the AMD microprocessor. System integration issues must be optimized to exploit this speedup in the overall simulation.

Monte Carlo radiative heat transfer simulation on a reconfigurable computer

Recently, the appearance of very large (3 – 10M gate) FPGAs with embedded arithmetic units has opened the door to the possibility of floating point computation on these devices. While previous researchers have described peak performance or kernel matrix operations, there is as yet relatively little experience with mapping an application-specific floating point loop onto FPGAs. In this work, we port a supercomputer application benchmark onto Xilinx Virtex II and Virtex II Pro FPGAs and compare performance with three Pentium IV Xeon microprocessors. Our results show that this application-specific pipeline, with 12 multiply, 10 add/subtract, one divide, and two compare modules of single precision floating point data type, shows speed up of 10.37×. We analyze the trade-offs between hardware and software to characterize the algorithms that will perform well on current and future FPGA architectures.

Partitioning Hardware and Software for Reconfigurable Supercomputing Applications: A Case Study

Often reconfigurable systems are reported to have 10× to 100× speedup over that of a software system. However, the reconfigurable hardware must usually be combined with software to form an entire system. This system integration presents a hardware/software co-design problem with many system engineering issues. Here, we present traffic acceleration on the Cray XD1 supercomputer and describe the costs involved in different hardware/software trade-offs.

Matched Filter Computation on FPGA, Cell and GPU

The matched filter is an important kernel in the processing of hyperspectral data. The filter enables researchers to sift useful data from instruments that span large frequency bands and can produce Gigabytes of data in seconds. In this work, we evaluate the performance of a matched filter algorithm implementation on an FPGA-accelerated co-processor (Cray XD-1), the IBM Cell microprocessor, and the NVIDIA GeForce 7900 GTX GPU graphics card. We provide extensive discussion of the challenges and opportunities afforded by each platform. In particular, we explore the problems of partitioning the filter most efficiently between the host CPU and the co-processor. Using our results, we derive several performance metrics that provide the optimal solution for a variety of application situations.

Single-Event Effects in Low-Cost, Low-Power Microprocessors

ARMs and microcontrollers are low-cost, low-power microprocessors that are frequently used in embedded computing. While not immune to the naturally occurring radiation environment in space, these microprocessors can be worthwhile replacements for space-grade microprocessors for non-mission-critical computational tasks. In this paper results from radiation testing for several available ARMs and microcontrollers are presented.

Compendium of TID, Neutron, Proton and Heavy Ion Testing of Satellite Electronics for Los Alamos National Laboratory

Los Alamos National Laboratory has been testing COTS electronic parts for potential use in spacecrafts. The highest risk parts were identified and tested for radiation effects.

The Reliability of Software Algorithms and Software-Based Mitigation Techniques in Digital Signal Processors

Digital signal processors (DSP) are microprocessor- like processing elements that are specifically designed for signal and image processing algorithms. DSPs share many of the same failure mechanisms as microprocessors, including component crashes, program crashes and silent data corruption (SDC). The root of these problems is often single- event upsets (SEUs) in caches or control circuitry. In testing we have found DSPs are very sensitive to SDC, where computationally incorrect output data is produced but program execution is not affected. SDC can be problematic as it is hard to detect and could lead to the corruption of on-orbit data. We found that SDC could be reduced through the use of triple modular redundancy. In this paper we present data on how software on DSPs is susceptible to radiation-induced upsets and software techniques for reducing SDC.

Software resilience and the effectiveness of software mitigation in microcontrollers

Commercially available microprocessors could be useful to the space community for noncritical computations. There are many possible components that are smaller, lower-power, and less expensive than traditional radiation-hardened microprocessors. Many commercial microprocessors have issues with single-event effects (SEEs), such as single-event upsets (SEUs) and single-event transients (SETs), that can cause the microprocessor to calculate an incorrect result or crash. In this paper we present the Trikaya technique for masking SEUs and SETs through software mitigation techniques. Test results show that this technique can be very effective at masking errors, making it possible to fly these microprocessors for a variety of missions.