Justin S. J. Wong

Degradation in FPGAs: measurement and modelling

Progress in VLSI technology is driven by increasing circuit density through process scaling, but with shrinking geometry comes an increasing threat to reliability. FPGAs are uniquely placed to tackle degradation and faults due to their regular structure and ability to reconfigure, giving them the potential to implement system-level reliability enhancements. To assess the scale of the challenge, a method for measuring and monitoring degradation in an FPGA was developed and used to conduct an accelerated life test on a modern device. This revealed a clear, gradual degradation in timing performance that matches the expected effects of Negative-Bias Temperature Instability and Hot Carrier Injection, two of the most important VLSI degradation mechanisms. Further insight into ageing phenomena was gained using modelling -- showing how degradation in a typical LUT would be affected by different usage conditions, and predicting in detail the effects on circuit behaviour.

Self-Measurement of Combinatorial Circuit Delays in FPGAs

This article proposes a Built-In Self-Test (BIST) method to accurately measure the combinatorial circuit delays on an FPGA. The flexibility of the on-chip clock generation capability found in modern FPGAs is employed to step through a range of frequencies until timing failure in the combinatorial circuit is detected. In this way, the delay of any combinatorial circuit can be determined with a timing resolution of the order of picoseconds. Parallel and optimized implementations of the method for self-characterization of the delay of all the LUTs on an FPGA are also proposed. The method was applied to Altera Cyclone II and III FPGAs . A complete self-characterization of LUTs on a Cyclone II was achieved in 2.5 seconds, utilizing only 13kbit of block RAM to store the results. More extensive tests were carried out on the Cyclone III and the delays of adder circuits and embedded multiplier blocks were successfully measured. This self-measurement method paves the way for matching timing requirements in designs to FPGAs as a means of combating the problem of process variations.

Degradation Analysis and Mitigation in FPGAs

FPGAs are powerful platforms for investigating impending challenges associated with process scaling, such as variation and degradation. Their versatility allows us to gather empirical data and evaluate novel solutions. We carried out accelerated-life tests on modern FPGA devices and obtained a useful characterisation of the ageing processes that afflict them. We also quantified the potential benefits of three degradation mitigation strategies based on exploiting spare logic and interconnect resources. The work helps cement the role of reconfigurable logic as a vitally-important technology in the face of the uncertainties of future process scaling.

Self-characterization of Combinatorial Circuit Delays in FPGAs

This paper proposes a built-in self-test (BIST) method to measure accurately the combinatorial circuit delays on an FPGA. The flexibility of the on-chip clock generation capability found in modern FPGAs is employed to step through a range of frequencies until timing failure in the combinatorial circuit is detected. In this way, the delay of any combinatorial circuit can be determined with a timing resolution of 1 ps or lower. A parallel implementation of the method for self-characterization of the delay of all the LUTs on an FPGA is also proposed. The method was applied to an Altera Cyclone-II FPGA (EP2C35). A complete self-characterization was achieved in 3 seconds, utilizing only 13 kbit of block RAM to store the results. This self-characterization method paves the way for matching timing requirements in designs to FPGAs as a means of combating the problem of process variations.

A transition probability based delay measurement method for arbitrary circuits on FPGAs

This paper proposes a novel test method for measuring the worst case path delay of any circuit on an FPGA, combinatorial or sequential, where little prior knowledge of the circuitpsilas internal structure is required. The method is based on detecting changes in the transition probability profile on the circuitpsilas output nodes while a range of test clock frequencies is stepped through. The method is applied to three classes of circuits, all implemented on an Altera Cyclone III FPGA: an adder carry chain, an embedded multiplier and a linear-feedback shift-register. The measured delays are compared to that found by a previously published, but much more time consuming, method and their results match to within 12%.

Characterisation of FPGA Clock Variability

As integrated circuits are scaled down it becomes difficult to maintain uniformity in process parameters across each individual die. The resulting performance variation requires new design strategies to avoid pessimistic over-design. A quantified understanding of the contribution different circuit components make to performance variation is a necessary part of such strategies. This paper proposes a technique for quantifying variability in clock skew in FPGAs based on a novel differential delay measurement circuit. The technique is capable of isolating the effects on clock skew from different components in the clock network. Results from a 65 nm FPGA show that clock skew variation is significant, being comparable in magnitude to signal path delay variation.

Improved delay measurement method in FPGA based on transition probability

The ability to measure delay of arbitrary circuits on FPGA offers many opportunities for on-chip characterisation and optimisation. This paper describes an improved delay measurement method by monitoring the transition probability at the output nodes as the operating frequency is swept. The new method uses optimised test vector generation to improve the accuracy of the test method. It is effectively demonstrated on a 4th order IIR filter circuit implemented on an Altera Cyclone III FPGA.

Variation and Reliability in FPGAs

This paper focuses on variability and reliability issues for FPGAs. The paper shows how these issues can be effectively addressed using one of the most powerful features of FPGAs: their ability and flexibility to be reconfigured. The paper also presents techniques for characterizing variability and degradation in these systems.

Modelling and compensating for clock skew variability in FPGAs

As integrated circuits are scaled down it becomes difficult to maintain uniformity in process parameters across each individual die. To avoid significant performance loss through pessimistic over-design new design strategies are required that are cognisant of within-die performance variability. This paper examines the effect of process variability on the clock resources in FPGA devices. A model of variation in clock skew in FPGA clock networks is presented. Techniques for reducing the impact of variations on the performance of implemented designs are proposed and analysed, demonstrating that skew variation can be reduced by 70% or more through a combination of phase adjustment and clock rerouting. Measurements on a Virtex-5 FPGA validate the feasibility and benefits of the proposed compensation strategies.

Combating process variation on FPGAS with a precise at-speed delay measurement method

The goal of this PhD project is to devise a way to combat the effect of process variation on propagation delays in modern FPGAs. Through our research, we have devised a novel measurement method that is capable of measuring the delays of components on FPGAs with picosecond timing resolution and fine spatial granularity. The method avoids the use of external test equipment and able to measure stochastic delay variability, which is becoming increasingly significant. The aim is to exhaustively test FPGA components based on this method and use the results to optimise the placement and routing of circuits in FPGAs to maximise performance under the negative influence of process variation.