Sumanta Chaudhuri

Security Evaluation of WDDL and SecLib Countermeasures against Power Attacks

Logic styles with constant power consumption are promising solutions to counteract side-channel attacks on sensitive cryptographic devices. Recently, one vulnerability has been identified in a standard-cell-based power-constant logic called WDDL. Another logic, nicknamed SecLib, is considered and does not present the flaw of WDDL. In this paper, we evaluate the security level of WDDL and SecLib. The methodology consists in embedding in a dedicated circuit one unprotected DES coprocessor along with two others, implemented in WDDL and in SecLib. One essential part of this paper is to describe the conception of the cryptographic ASIC, devised to foster side-channel cryptanalyses, in a view to model the strongest possible attacker. The same analyses are carried out successively on the three DES modules. We conclude that, provided that the back-end of the WDDL module is carefully designed, its vulnerability cannot be exploited by the state-of-the-art attacks. Similarly, the SecLib DES module resists all assaults. However, using a principal component analysis, we show that WDDL is more vulnerable than SecLib. The statistical dispersion of WDDL, which reflects the correlation between the secrets and the power dissipation, is proved to be an order of magnitude higher than that of SecLib.

Place-and-route impact on the security of DPL designs in FPGAs

Straightforward implementations of cryptographic algorithms are known to be vulnerable to attacks aimed not at the mathematical structure of the cipher but rather at the weak points of the electronic devices which implement it. These attacks, known as side-channel attacks, have proved to be very powerful in retrieving secret keys from any kind of unprotected electronic device. Amongst the various protection strategies, side-channel hiding is very popular and well studied. The principle of information hiding is to make any leak constant, thus uncorrelated to the device internal secrets. The so-called ldquodual-rail with precharge logicrdquo (DPL) style is indicated to achieve that goal. For DPL protection to be effective, it further requires a carefully balanced layout so as to obtain equal propagation delays and power consumption on both rails. In this article, we study to which extent the differential place-and-route constraints must be strict in FPGA technology. We describe placement techniques suitable for Xilinx and Altera FPGAs, and quantify the gain of balance they confer. On the one hand, we observed that Xilinx fitting tool achieves naturally good balancing results. On the other hand, the symmetry can be greatly improved with Altera devices, using a manual placement, leading to unprecedented dual netlists balancing.

Physical Design of FPGA Interconnect to Prevent Information Leakage

In this article we discuss dual/multi-rail routing techniques in an island style FPGA for robustness against side-channel attacks. We present a technique to achieve dual-rail routing balanced in both timing and power consumption with the traditional subset switchbox. Secondly, we propose two switchboxes (namely: Twist-on-Turn & Twist-Always) to route every dual/multi-rail signal in twisted pairs, which can deter electromagnetic attacks. These novel switchboxes can also be balanced in power consumption albeit with some added cost. We present a layout with pre-placed switches and pre-routed balanced wires and extraction statistics about the expected balance. As conclusion, we discuss various overheads associated with these techniques and possible improvements.

High Density Spin-Transfer Torque (STT)-MRAM Based on Cross-Point Architecture

Spin transfer torque magnetic random access memory (STT-MRAM) is considered as one of the most promising candidates to build up a true universal memory thanks to its fast write/read speed, infinite endurance and non-volatility. However the conventional access architecture based on 1 transistor + 1 memory cell limits its storage density as the selection transistor should be large enough to ensure the write current higher than the critical current for the STT operation. This paper describes a design of cross-point architecture for STT-MRAM. The mean area per word corresponds to only two transistors, which are shared by a number of bits (e.g. 64). This leads to significant improvement of data density (e.g. 1.75 F2/bit). Special techniques are also presented to address the sneak currents and low speed issues of conventional cross-point architecture.

Design of TAS-MRAM prototype for NV embedded memory applications

In this paper, we present a new design of TAS-MRAM, which is dedicated for the embedded applications. The Thermally Assisted Switching (TAS) approach allows the low power memory programming and Pre-Charge Sense Amplifiers (PCSA) enable the reliable, high speed and low power sensing. By using a TAS-MTJ spice model integrating the precise experimental parameters and CMOS 130nm technology, simulations have been done to demonstrate the expected performances; a 128Kb prototype has been developed to validate experimentally the new design by means of standard cell and automatic macro generation techniques.

High Density Asynchronous LUT Based on Non-volatile MRAM Technology

In this article, we present the architecture design of high-performance Asynchronous Look Up Table (LUT) embedded with a non-volatile Magnetic RAM (MRAM) as the configuration memory, called MALUT. It promises a number of advantages over the traditional FPGA circuits such as “free” standby power, high operating frequency and instant on/off etc. Thanks to the 3D integration and high density of MRAM, fine-grain run-time reconfiguration and multi-context configuration can be achieved. An automatic design flow has been developed for the design of complex hybrid CMOS/MRAM circuits. Based on CMOS 130nm and MRAM 120nm technology, mixed simulations and layout implementation have been done to demonstrate the expected operation and configuration performances. At last, we discuss and conclude.

An 8×8 run-time reconfigurable FPGA embedded in a SoC

This paper presents a RTR FPGA embedded in a system on chip fabricated in 130 nm CMOS process. Various aspects of the design flow, from automation to floor-planning are discussed. We explain the measures taken in the FPGA design to guarantee RTR functionality free of electrical conflicts, and we present a flow based on Altera synthesis tools to implement IPs(hardware blocks) in this FPGA. We demonstrate the full functionality with experiments on the FPGA, and as conclusion we highlight the limitations and future research directions.

A Novel Asynchronous e-FPGA Architecture for Security Applications

With the growing security needs of applications such as homeland security or banking, the frequent updates in cryptographic standards and the high ASIC costs, the ciphering algorithms on an asynchronous embedded FPGA co-processor are becoming a viable alternative. Within the SAFE project, a novel architecture of asynchronous e-FPGA has been proposed. This architecture is natively robust against side channel attacks such as simple and differential power analysis or clock based fault attacks. Simulation-based security proofs are also presented.

FASE: An Open Run-Time Reconfigurable FPGA Architecture for Tamper-Resistant and Secure Embedded Systems

The run-time reconfigurable (RTR) feature is highly desirable for flexible and fast self-contained systems. RTR can be achieved on some commercial FPGA platforms. We propose an open solution, called FASE that allows for fine-grain RTR, designed to be more intuitive than currently available solutions. The issues of initializing RTR soft IP-cores and a design flow to manage the dynamics of RTR are presented. In the context of secure embedded systems, there is a need for both flexibility and tamper-resistance. However, the robustness level for security constraints is difficult to get and to prove because of the proprietary hidden structures. The FASE architecture addresses these issues. It makes it possible for any designer to implement custom and arbitrary dynamic strategies. We illustrate two case studies: an implementation-level counter-measure against side-channel attacks and an efficient strategy to thwart fault injection attacks against cryptographic functions

Design of embedded MRAM macros for memory-in-logic applications

In this article we present a design method for integrating non-volatile MRAM memory cells into standard CMOS design. The emphasis is on standard cell based flow for general purpose logic and automatic generation or MRAM macros suitable for the applications. We present a design space exploration for this purpose and transient simulation results of the hybrid MTJ/CMOS designs. We continue the article with examples of automatic macro generation, integration layout and a prototype in 130nm CMOS which is designed to test a large subset of this design space. In conclusion we show that a high 3D integration density with reasonable speed can be achieved with automatic flow by sharing the reading/writing circuitry among a number of MTJs.