Jyh-Chyurn Guo

A new approach to determine the effective channel length and the drain-and-source series resistance of miniaturized MOSFET's

A new decoupled C-V method is proposed to determine the intrinsic (effective) channel region and extrinsic overlap region for miniaturized MOSFETs. In this approach, a unique channel-length-independent extrinsic overlap region is extracted at a critical gate bias, so bias-independent effective channel lengths (L/sub eff/) are achieved. Furthermore, the two-dimensional (2D) charge sharing effect is separated from the effective channel region. Based on this L/sub eff/ and the associated bias-dependent channel mobility, /spl mu//sub eff/, the drain-and-source series resistance (R/sub DS/) can be derived from the I-V characteristics for each device individually. For the first time, the assumption or approximation for R/sub DS/ and /spl mu//sub eff/ can be avoided, thus the difficulties and controversy encountered in the conventional I-V method can be solved. The 2D charge sharing effect is incorporated into the bias-dependent R/sub DS/. This bias dependence is closely related to the drain/source doping profile and the channel dopant concentration. The proposed L/sub eff/ and R/sub DS/ extraction method has been verified by an analytical I-V model which shows excellent agreements with the measured I-V characteristics. >

A broadband and scalable model for on-chip inductors incorporating substrate and conductor loss effects

A new T-model is developed to accurately simulate the broadband characteristics of on-Si-chip spiral inductors, up to 20 GHz. The spiral coil and substrate RLC networks built in the model play a key role responsible for conductor loss and substrate loss in the wideband regime, which cannot be accurately described by the conventional /spl pi/-model. Good match with the measured S-parameters, L(/spl omega/), Re(Z/sub in/(/spl omega/)), and Q(/spl omega/) proves the proposed T-model. Besides the broadband feature, scalability is justified by the good match with a linear function of coil numbers for all model parameters employed in the RLC networks. The satisfactory scalability manifest themselves physical parameters rather than curve fitting. A parameter extraction flow is established through equivalent circuit analysis to enable automatic parameter extraction and optimization. This scalable inductor model will facilitate optimization design of on-chip inductor and the accuracy proven up to 20 GHz can improve RF circuit simulation accuracy demanded by broadband design.

Pocket implantation effect on drain current flicker noise in analog nMOSFET devices

The pocket implantation effect on drain current flicker noise in 0.13 /spl mu/m CMOS process based high performance analog nMOSFETs is investigated. Our result shows that pocket implantation will significantly degrade device low-frequency noise primarily because of nonuniform threshold voltage distribution along the channel. An analytical flicker noise model to account for a pocket doping effect is proposed. In our model, the local threshold voltage and the width of the pocket implant region are extracted from the measured reverse short-channel effect, and the oxide trap density is extracted from a long-channel device. Good agreement between our model and the measurement result is obtained without other fitting parameters.

A three-terminal band-trap-band tunneling model for drain engineering and substrate bias effect on GIDL in MOSFET

A new three-terminal partial band-trap-band tunneling (BTB) model is proposed to predict the drain engineering effect and substrate bias effect on gate-induced-drain-leakage (GIDL) characteristics for virgin devices free from electric stress. The lateral field /spl epsiv//sub L/ and the ratio of lateral field w.r.t. total field /spl epsiv/(/spl epsiv//sub L///spl epsiv/) are two key factors responsible for the tunneling barrier lowering and the enhancement of GIDL. The principle to suppress GIDL are two-fold: the first one is to eliminate process induced intrinsic interface states and the second one is to minimize /spl epsiv//sub L/ and /spl epsiv//sub L///spl epsiv/ by using drain engineering or changing bias conditions such as applying forward substrate biases.

Narrow-Width Effect on High-Frequency Performance and RF Noise of Sub-40-nm Multifinger nMOSFETs and pMOSFETs

The impact of narrow-width effects on high-frequency performance like <i>fT</i>, <i>f</i>_MAX, and RF noise parameters, such as <i>NF</i>_min and <i>Rn</i>, in sub-40-nm multifinger CMOS devices is investigated in this paper. Narrow-oxide-diffusion (OD) MOSFET with smaller finger width and larger finger number can achieve lower <i>Rg</i> and higher <i>f</i>_MAX. However, these narrow-OD devices suffer <i>fT</i> degradation and higher <i>NF</i>_min, even with the advantage of lower <i>Rg</i>. The mechanisms responsible for the tradeoff between different parameters will be presented to provide an important guideline of multifinger MOSFET layout for RF circuit design using nanoscale CMOS technology.

A Broadband and Scalable On-Chip Inductor Model Appropriate for Operation Modes of Varying Substrate Resistivities

A broadband and scalable model is developed to accurately simulate on-chip inductors of various dimensions and substrate resistivities. The broadband accuracy is proven over frequencies up to 20 GHz, even beyond resonance. A new scheme of RLC networks is deployed for spiral coils and substrate to account for 3D eddy current, substrate return path, and spiral coil to substrate coupling effects, etc. The 3D eddy current is identified as the key element essential to accurately simulate broadband characteristics. EM simulation using ADS momentum is conducted to predict the on-chip inductor performance corresponding to wide range of substrate resistivities (rhoSi=0.05~KOmega-cm). Three operation modes such as TEM, slow-wave, and eddy current are reproduced. The model parameters manifest themselves physics-base through relevant correlation with rhoSi over three operation modes. The onset of slow-wave mode can be consistently explained by a key element (RP) introduced in our model, which accounts for the conductor loss due to eddy current arising from magnetic field coupling through substrate return path. This broadband and scalable model is useful for RF circuit simulation. Besides, it can facilitate optimization design of on-chip inductors through physics-based model parameters relevant to varying substrate resistivities

A New Lossy Substrate Model for Accurate RF CMOS Noise Extraction and Simulation With Frequency and Bias Dependence

A lossy substrate model is developed to accurately simulate the measured RF noise of 80-nm super-100-GHz fT n-MOSFETs. A substrate RLC network built in the model plays a key role responsible for the nonlinear frequency response of noise in 1-18-GHz regime, which did not follow the typical thermal noise theory. Good match with the measured S-parameters, Y-parameters, and noise parameters before deembedding proves the lossy substrate model. The intrinsic RF noise can be extracted easily and precisely by the lossy substrate deembedding using circuit simulation. The accuracy has been justified by good agreement in terms of Id,gm, Y-parameters, and f T under a wide range of bias conditions and operating frequencies. Both channel thermal noise and resistance induced excess noises have been implemented in simulation. A white noise gamma factor extracted to be higher than 2/3 accounts for the velocity saturation and channel length modulation effects. The extracted intrinsic NFmin as low as 0.6-0.7 dB at 10 GHz indicates the advantages of super-100 GHz fT offered by the sub-100-nm multifinger n-MOSFETs. The frequency dependence of noise resistance Rn suggests the bulk RC coupling induced excess channel thermal noise apparent in 1-10-GHz regime. The study provides useful guideline for low noise and low power design by using sub-100-nm RF CMOS technology

The Impact of Layout-Dependent STI Stress and Effective Width on Low-Frequency Noise and High-Frequency Performance in Nanoscale nMOSFETs

The impact of channel width scaling on low-frequency noise (LFN) and high-frequency performance in multifinger MOSFETs is reported in this paper. The compressive stress from shallow trench isolation (STI) cannot explain the lower LFN in extremely narrow devices. STI top corner rounding (TCR)-induced Δ<i>W</i> is identified as an important factor that is responsible for the increase in transconductance <i>Gm</i> and the reduction in LFN with width scaling to nanoscale regime. A semi-empirical model was derived to simulate the effective mobility (μ_eff) degradation from STI stress and the increase in effective width (<i>W</i>_eff) from Δ<i>W</i> due to STI TCR. The proposed model can accurately predict width scaling effect on <i>Gm</i> based on a tradeoff between μ_eff and <i>W</i>_eff. The enhanced STI stress may lead to an increase in interface traps density (<i>N</i>_it), but the influence is relatively minor and can be compensated by the <i>W</i>_eff effect. Unfortunately, the extremely narrow devices suffer <i>fT</i> degradation due to an increase in <i>C</i>_gg. The investigation of impact from width scaling on μ_eff, <i>Gm</i>, and LFN, as well as the tradeoff between LFN and high-frequency performance, provides an important layout guideline for analog and RF circuit design.

Ultra-low voltage and low power UWB CMOS LNA using forward body biases

An ultra-wideband (UWB) low noise amplifier (LNA) was designed and fabricated using 0.18μm 1.8V CMOS technology. The adoption of forward body biases (FBB) in a 3-stage distributed amplifier enables an aggressive scaling of the supply voltages and gate input voltage to 0.6V. The low voltage feature from FBB leads to more than 50% power consumption saving to 4.2mW. The measured power gain (S21) is higher than 10dB in 3.1~8.1GHz and noise figure is 2.83~4.7 dB in the wideband of 2~10GHz. Superior linearity is achieved with IIP3 as high as 4.2dBm and 12.5dBm at 6.5GHz and 10GHz, respectively.

A New Three-Dimensional Capacitor Model for Accurate Simulation of Parasitic Capacitances in Nanoscale MOSFETs

A new 3-D gate capacitor model is developed to accurately calculate the parasitic capacitances of nanoscale CMOS devices. The dependences on gate length and width, gate electrode and dielectric thicknesses, gate-to-contact spacing, and contact dimension and geometry are fully incorporated in this model. The accuracy is certified by an excellent match with the 3-D interconnection simulation results for three structures with strip, square, and circular contacts. The features of being free from fitting parameters and proven accuracy over various geometries make this model useful for nanoscale MOSFET parasitic capacitance simulation and analysis. Furthermore, the developed capacitor model in the form of multidimensional integral can easily be deployed in general circuit simulators. This model predicts that the parasitic capacitance C of dominates around 25% of the intrinsic gate capacitance (C gint) in 80-nm MOSFETs and that the near nonscalability with gate length brings the weighting factor C of/C gint above 30%/40%/60% in 65-/45-/32-nm devices. It actually exceeds the limitation defined by the most updated ITRS and reveals itself as a show-stopper in high-speed and high-frequency circuit design.