Kuo-Liang Yeh

Narrow-Width Effect on High-Frequency Performance and RF Noise of Sub-40-nm Multifinger nMOSFETs and pMOSFETs

The impact of narrow-width effects on high-frequency performance like <i>fT</i>, <i>f</i>_MAX, and RF noise parameters, such as <i>NF</i>_min and <i>Rn</i>, in sub-40-nm multifinger CMOS devices is investigated in this paper. Narrow-oxide-diffusion (OD) MOSFET with smaller finger width and larger finger number can achieve lower <i>Rg</i> and higher <i>f</i>_MAX. However, these narrow-OD devices suffer <i>fT</i> degradation and higher <i>NF</i>_min, even with the advantage of lower <i>Rg</i>. The mechanisms responsible for the tradeoff between different parameters will be presented to provide an important guideline of multifinger MOSFET layout for RF circuit design using nanoscale CMOS technology.

The Impact of Layout-Dependent STI Stress and Effective Width on Low-Frequency Noise and High-Frequency Performance in Nanoscale nMOSFETs

The impact of channel width scaling on low-frequency noise (LFN) and high-frequency performance in multifinger MOSFETs is reported in this paper. The compressive stress from shallow trench isolation (STI) cannot explain the lower LFN in extremely narrow devices. STI top corner rounding (TCR)-induced Δ<i>W</i> is identified as an important factor that is responsible for the increase in transconductance <i>Gm</i> and the reduction in LFN with width scaling to nanoscale regime. A semi-empirical model was derived to simulate the effective mobility (μ_eff) degradation from STI stress and the increase in effective width (<i>W</i>_eff) from Δ<i>W</i> due to STI TCR. The proposed model can accurately predict width scaling effect on <i>Gm</i> based on a tradeoff between μ_eff and <i>W</i>_eff. The enhanced STI stress may lead to an increase in interface traps density (<i>N</i>_it), but the influence is relatively minor and can be compensated by the <i>W</i>_eff effect. Unfortunately, the extremely narrow devices suffer <i>fT</i> degradation due to an increase in <i>C</i>_gg. The investigation of impact from width scaling on μ_eff, <i>Gm</i>, and LFN, as well as the tradeoff between LFN and high-frequency performance, provides an important layout guideline for analog and RF circuit design.

A New Method for Layout-Dependent Parasitic Capacitance Analysis and Effective Mobility Extraction in Nanoscale Multifinger MOSFETs

The impact of layout-dependent parasitic capacitances on extraction of inversion carrier density <i>Q</i>_inv and effective mobility μ_eff has been investigated on multifinger MOSFETs. An improved open deembedding method can eliminate the extrinsic parasitic capacitance, and 3-D interconnect simulation is necessary for extraction of intrinsic parasitic capacitances such as gate finger sidewall and finger-end fringing capacitances, i.e., <i>C</i>_of and <i>Cf</i>(poly-end), respectively. Both categories of parasitic capacitance lead to overestimated <i>Q</i>_inv and underestimated μ_eff. The increase in effective channel width <i>W</i>_eff due to Δ<i>W</i> from shallow trench isolation (STI) top-corner rounding may compensate μ_eff degradation due to STI stress. The tradeoff between μ_eff and <i>W</i>_eff determines the impact of width scaling on <i>I</i>_DS and <i>Gm</i> . A new method based on the measured S-parameters, open-M1 deembedding, and Raphael simulation can precisely determine the mentioned parameters associated with the intrinsic channel and realize accurate extraction of μ_eff in multifinger MOSFETs with various layouts and narrow widths down to 0.125 μm.

Layout-Dependent Stress Effect on High-Frequency Characteristics and Flicker Noise in Multifinger and Donut MOSFETs

The impact of MOSFET layout-dependent stress on high-frequency performance and flicker noise has been investigated. The proposed donut MOSFETs demonstrate the advantages over the standard multifinger MOSFETs, such as the lower flicker noise SID/IDS2 in the low-frequency domain and the higher cutoff frequency fT in the very high-frequency region. The elimination of the transverse stress σ⊥ from shallow trench isolation (STI) and the suppression of interface traps along the STI edge are proposed as the primary factors responsible for the enhancement of the effective mobility μeff, as well as fT, and the reduction of flicker noise. The significantly lower flicker noise realized by donut devices suggests the reduction of STI-generated traps and the suppression of mobility fluctuation due to eliminated transverse stress. The former is applied to n-channel MOS in which the flicker noise is determined by the number-fluctuation model. The latter is responsible for p-channel MOS whose flicker noise is dominated by the mobility-fluctuation model.

Layout-dependent effects on high frequency performance and noise of sub-40nm multi-finger n-channel and p-channel MOSFETs

Layout dependent effects on high frequency performance parameters like f<inf>T</inf>, f<inf>MAX</inf>, and RF noise in sub-40nm multi-finger MOSFETs is investigated in this paper. Narrow-OD MOSFET with smaller finger width and larger finger number can achieve lower R<inf>g</inf> and higher f<inf>MAX</inf>. However, these narrow-OD devices suffer f<inf>T</inf> degradation and higher noise figure, even with the advantage of lower R<inf>g</inf>. The mechanisms responsible for the trade-off between different parameters will be presented to provide an important guideline of device layout for RF circuits design using nanoscale CMOS technology.

Layout Dependent STI Stress Effect on High Frequency Performance and Flicker Noise in Nanoscale CMOS Devices

The impact of MOSFET layout dependent stress on high frequency performance and flicker noise is investigated. The proposed donut MOSFETs demonstrate the advantages over the standard MOSFETs, such as the lowest SID/IDS in low frequency domain and higher fT in very high frequency region. The elimination of the transverse stress from shallow trench isolation (STI) and excess traps along the gate width is validated as the primary mechanism responsible for the enhancement of μeff as well as fT, and the reduction of flicker noise. The layout dependent stress mechanism can be applied to both NMOS and PMOS, while their flicker noises are governed by number fluctuation model and mobility fluctuation model, respectively.

The Impact of Uni-axial Strain on Low Frequency Noise in Nanoscale p-Channel Metal–Oxide–Semiconductor Field Effect Transistors under Dynamic Body Biases

The impact of local strain on low frequency noise (LFN) in p-channel metal–oxide–semiconductor field effect transistor (pMOSFET) is investigated under dynamic body biases. For 60 nm pMOSFET, the uni-axial compressive strain from embedded SiGe (e-SiGe) in source/drain can contribute 75% effective mobility (µeff) enhancement and the proportional improvement in current (IDS) as well as transconductance (Gm). However, the strained pMOSFET suffer more than 80% higher LFN (SID/ID2) compared with the control pMOSFET free from strain engineering. The measured LFN can be consistently explained by mobility fluctuation model and the increase of Hooge parameter (αH) appears as a key factor responsible for the higher LFN in strained pMOSFET. Forward body biases (FBB) is proposed as an effective method adapted to nanoscale devices for improving µeff and suppressing LFN, without resort to strain engineering.

Flicker noise in nanoscale pMOSFETs with mobility enhancement engineering and dynamic body biases

The uni-axial compressive strain from e-SiGe S/D combined with dynamic body biases effect on flicker noise of pMOSFETs is presented in this paper. This compressive strain contributes higher mobility but the worse flicker noise in terms of higher SID/ID2 becomes a potential killer to RF/analog circuits. Forward body biases (FBB) can reduce the flicker noise but the degraded body bias effect in strained pMOSFETs makes it not as efficient as the standard ones without strain. Hooges mobility fluctuation model is adopted to explain the uni-axial strain and dynamic body biases effect on flicker noise. The increase of Hooge parameter αH is identified the key factor responsible the degraded flicker noise in strained pMOSFETs.

Low frequency noise in nanoscale pMOSFETs with strain induced mobility enhancement and dynamic body biases

Local strain effect on low frequency noise (LFN) of pMOSFETs with gate length down to 60 nm was investigated in this paper. Novel and interesting results were identified from the pMOSFETs adopting embedded SiGe (e-SiGe) in source/drain for uni-axial compressive stress. This local compressive strain can realize significant mobility enhancement and desired current boost in nanoscale pMOSFETs. However, the dramatic increase of LFN emerges as a penalty traded off with mobility enhancement. The escalated LFN may become a critical killer to analog and RF circuits. Forward body biases (FBB) can improve the effective mobility (μeff) and reduce LFN attributed to reduced normal field (Eeff). However, the benefit from FBB becomes insignificant in strained pMOSFETs with sub-100 nm gate length.

The Trade-off between STI Stress and Gate Resistance in RF MOSFETs Design for High Frequency Performance and RF Noise

STI stress induced mobility and transconductance (g m) degradation appear as a penalty of multi-finger dev ices for RF and analog design. Donut device layout is proposed to e liminate the STI transverse stress and achieve higher g m. Both NMOS and PMOS can benefit from the donut layout, with higher cut-off frequency (f T). However, the trade-off between g m and gate resistance (Rg) may impose undesired impact on high frequency performance other than f T, such as maximum oscillation frequency (fmax) and RF noise. In this paper, a comparison between multi-finger and donut MOSFETs in terms of f T, max, and NFmin can provide a useful guideline of device layout for RF design using nanoscale CMOS technology.