Jyotica V. Patel

Looking into the crystal ball: future device learning using hybrid e-beam and optical lithography (Keynote Paper)

Semiconductor process development teams are faced with increasing process and integration complexity while the time between lithographic capability and volume production has remained more or less constant over the last decade. Lithography tools have often gated the volume checkpoint of a new device node on the ITRS roadmap. The processes have to be redeveloped after the tooling capability for the new groundrule is obtained since straight scaling is no longer sufficient. In certain cases the time window that the process development teams have is actually decreasing. In the extreme, some forecasts are showing that by the time the 45nm technology node is scheduled for volume production, the tooling vendors will just begin shipping the tools required for this technology node. To address this time pressure, IBM has implemented a hybrid-lithography strategy that marries the advantages of optical lithography (high throughput) with electron beam direct write lithography (high resolution and alignment capability). This hybrid-lithography scheme allows for the timely development of semiconductor processes for the 32nm node, and beyond. In this paper we will describe how hybrid lithography has enabled early process integration and device learning and how IBM applied e-beam & optical hybrid lithography to create the worlds smallest working SRAM cell.

Hydrodynamics of Diamond-Shaped Gradient Nanopillar Arrays for Effective DNA Translocation into Nanochannels

Effective DNA translocation into nanochannels is critical for advancing genome mapping and future single-molecule DNA sequencing technologies. We present the design and hydrodynamic study of a diamond-shaped gradient pillar array connected to nanochannels for enhancing the success of DNA translocation events. Single-molecule fluorescence imaging is utilized to interrogate the hydrodynamic interactions of the DNA with this unique structure, evaluate key DNA translocation parameters, including speed, extension, and translocation time, and provide a detailed mapping of the translocation events in nanopillar arrays coupled with 10 and 50 μm long channels. Our analysis reveals the important roles of diamond-shaped nanopillars in guiding DNA into as small as 30 nm channels with minimized clogging, stretching DNA to nearly 100% of their dyed contour length, inducing location-specific straddling of DNA at nanopillar interfaces, and modulating DNA speeds by pillar geometries. Importantly, all critical features down to 30 nm wide nanochannels are defined using standard photolithography and fabrication processes, a feat aligned with the requirement of high-volume, low-cost production.

Wafer-scale integration of sacrificial nanofluidic chips for detecting and manipulating single DNA molecules

Wafer-scale fabrication of complex nanofluidic systems with integrated electronics is essential to realizing ubiquitous, compact, reliable, high-sensitivity and low-cost biomolecular sensors. Here we report a scalable fabrication strategy capable of producing nanofluidic chips with complex designs and down to single-digit nanometre dimensions over 200 mm wafer scale. Compatible with semiconductor industry standard complementary metal-oxide semiconductor logic circuit fabrication processes, this strategy extracts a patterned sacrificial silicon layer through hundreds of millions of nanoscale vent holes on each chip by gas-phase Xenon difluoride etching. Using single-molecule fluorescence imaging, we demonstrate these sacrificial nanofluidic chips can function to controllably and completely stretch lambda DNA in a two-dimensional nanofluidic network comprising channels and pillars. The flexible nanofluidic structure design, wafer-scale fabrication, single-digit nanometre channels, reliable fluidic sealing and low thermal budget make our strategy a potentially universal approach to integrating functional planar nanofluidic systems with logic circuits for lab-on-a-chip applications.

Integration of Photo-Patternable Low-κ Material into Advanced Cu Back-End-Of-The-Line

We report herein the demonstration of a simple, low-cost Cu back-end-of-the-line (BEOL) dual-damascene integration using a novel photo-patternable low-κ dielectric material concept that dramatically reduces Cu BEOL integration complexity. This κ=2.7 photo-patternable low-κ material is based on the SiCOH-based material platform and has sub-200 nm resolution capability with 248 nm optical lithography. Cu/photo-patternable low-κ dual-damascene integration at 45 nm node BEOL fatwire levels has been demonstrated with very high electrical yields using the current manufacturing infrastructure. The photo-patternable low-κ concept is, therefore, a promising technology for highly efficient semiconductor Cu BEOL manufacturing.

Narrow-channel accumulated-body bulk Si MOSFETs with wide-range dynamic threshold voltage tuning

Side-gated bulk Si nMOSFETs with Si3N4 shallow trench isolation (STI) have been previously demonstrated to have significantly reduced off-currents and improved subthreshold characteristics [1, 2]. The improvement is shown to be due to accumulation of the Si body with the holes as the polysilicon side-gate surrounding the body as a guard ring is negatively biased (Fig 1). The threshold voltage (VT) of the narrow channel devices can be dynamically controlled by the side-gate (Fig 2) voltage (Vside) in a wide range [2, 3], mainly due to the increase in the channel energy barrier (Fig. 3) [4]. Here, we report experimental results on narrow bulk Si accumulated body n-channel FETs with SiO2 side-gate dielectric and STI and p-type side-gates (Fig 2). The fabrication is compatible with established front and back end-of-line processes with only an added side-gate formation and side-gate contact step over conventional FET fabrication. 9 nm thermal SiO2 serves as the side-gate dielectric and 3.6 nm thermal SiO2 is used as gate dielectric. Final body doping is estimated to be at 1 x 1017 cm-3 (Boron). Gate, side-gate, source and drain have high n+ doping (~1 x 1020 cm-3).

Investigation of electrostatic body control in accumulated body MOSFETs

The authors previously reported wide-range threshold voltage (VT) control and improvement in subthreshold slope (SS) and drain induced barrier lowering (DIBL) in narrow bulk Si Accumulated Body MOSFETs [1-3]. The side-gate structure surrounding the MOSFET body is used for accumulating the body through an independent contact to provide these effects (Fig. 1). In this work, we present a study on the electrostatic body control attained by the side-gates, using experimental and simulated devices.

Silicon on Insulator CMOS with Hybrid Crystal Orientation Using Double Wafer Bonding

Carrier transport depends critically on MOSFET channel orientation, with electron mobility highest on the conventional Si (100) surface while hole mobility is more than 2x enhanced on the Si (110) surface [1]. CMOS on substrates composed of multiple surface orientations have been demonstratednFETs on the (100) surface orientation and pFETs on the (110) surface orientation -yielding pFET drive current enhancement of 30% at 45nm channel length [2]. However, in most of the previous publications on Hybrid Orientation Technology (HOT), nFETs were fabricated on silicon-on-insulator (SOI), but pFETs were bulk-like. The implementation of this HOT technology is therefore limited by the design changes during technology transfer. Furthermore, it is known that CMOS on SOI provides higher performance than conventional bulk device due the elimination of area junction capacitance (Cja), the lack of a reverse body effect in stacked circuits and the slightly forward biased SOI body under the nominal operating voltage range. In this paper, we present a novel SOI CMOS structure on hybrid orientation substrates through double wafer bonding.