Steven E. Steen

Three-dimensional integrated circuits

Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to dramatically enhance chip performance, functionality, and device packing density. They also provide for microchip architecture and may facilitate the integration of heterogeneous materials, devices, and signals. However, before these advantages can be realized, key technology challenges of 3D ICs must be addressed. More specifically, the processes required to build circuits with multiple layers of active devices must be compatible with current state-of-the-art silicon processing technology. These processes must also show manufacturability, i.e., reliability, good yield, maturity, and reasonable cost. To meet these requirements, IBM has introduced a scheme for building 3D ICs based on the layer transfer of functional circuits, and many process and design innovations have been implemented. This paper reviews the process steps and design aspects that were developed at IBM to enable the formation of stacked device layers. Details regarding an optimized layer transfer process are presented, including the descriptions of 1) a glass substrate process to enable through-wafer alignment; 2) oxide fusion bonding and wafer bow compensation methods for improved alignment tolerance during bonding; 3) and a single-damascene patterning and metallization method for the creation of high-aspect-ratio (6:1 108 vias/cm2), and extremely aggressive wafer-to-wafer alignment (submicron) capability.

Electrical characterization of germanium p-channel MOSFETs

In this letter, we report germanium (Ge) p-channel MOSFETs with a thin gate stack of Ge oxynitride and low-temperature oxide (LTO) on bulk Ge substrate without a silicon (Si) cap layer. The fabricated devices show 2 /spl times/ higher transconductance and /spl sim/ 40% hole mobility enhancement over the Si control with a thermal SiO/sub 2/ gate dielectric, as well as the excellent subthreshold characteristics. For the first time, we demonstrate Ge MOSFETs with less than 100-mV/dec subthreshold slope.

Enabling SOI-based assembly technology for three-dimensional (3d) integrated circuits (ICs)

We present solutions to the key process technology challenges of three-dimensional (3D) integrated circuits (ICs) that enable creation of stacked device layers with the shortest distance between them, the highest interconnection density and extremely aggressive wafer-to-wafer alignment. To achieve this important 3D IC technology milestone, we optimized the layer transfer process to include a glass handle wafer, oxide fusion bonding, wafer bow compensation methods, and a single damascene patterning and metallization method for creation of high-aspect-ratio (6:1 < AR < 11:1) contacts between two stacked device layers

The over-bump applied resin wafer-level underfill process: Process, material and reliability

The over bump applied resin (OBAR) process is a wafer-level underfill (WLUF) process in which a filled resin is applied over the bumps of a wafer and, dried. The wafer is diced into coated chips which are aligned and joined to a substrate resulting in an underfilled flip chip package. This process has been evaluated by IBM on several test vehicles in close cooperation with Henkel (formerly Abelstik) who developed a material specifically to fit this process. The critical steps to make this technology work are alignment of OBAR coated chip to a substrate, elimination of significant voids, formation of a fillet with appropriate shape and size, fluxing and solder joining. The reliability of the material was evaluated after capping and BGA (Ball Grid Array) attach through JEDEC level 3 preconditioning followed by DTC (deep thermal cycling), T&H (temperature and humidity), and HTS (high temperature storage). While some improvements are still needed, the OBAR process has been shown to be a viable alternative to capillary underfill application.

Looking into the crystal ball: future device learning using hybrid e-beam and optical lithography (Keynote Paper)

Semiconductor process development teams are faced with increasing process and integration complexity while the time between lithographic capability and volume production has remained more or less constant over the last decade. Lithography tools have often gated the volume checkpoint of a new device node on the ITRS roadmap. The processes have to be redeveloped after the tooling capability for the new groundrule is obtained since straight scaling is no longer sufficient. In certain cases the time window that the process development teams have is actually decreasing. In the extreme, some forecasts are showing that by the time the 45nm technology node is scheduled for volume production, the tooling vendors will just begin shipping the tools required for this technology node. To address this time pressure, IBM has implemented a hybrid-lithography strategy that marries the advantages of optical lithography (high throughput) with electron beam direct write lithography (high resolution and alignment capability). This hybrid-lithography scheme allows for the timely development of semiconductor processes for the 32nm node, and beyond. In this paper we will describe how hybrid lithography has enabled early process integration and device learning and how IBM applied e-beam & optical hybrid lithography to create the worlds smallest working SRAM cell.

Laterally scaled Si-Si/sub 0.7/Ge/sub 0.3/ n-MODFETs with f/sub max/>200 GHz and low operating bias

We report on the dc and RF characterization of laterally scaled, Si-SiGe n-MODFETs. Devices with gate length, L/sub g/, of 80 nm had f/sub T/=79 GHz and f/sub max/=212 GHz, while devices with L/sub g/=70 nm had f/sub T/ as high as 92 GHz. The MODFETs displayed enhanced f/sub T/ at reduced drain-to-source voltage, V/sub ds/, compared to Si MOSFETs with similar f/sub T/ at high V/sub ds/.

Scaling of Silicon Phase-Change Oscillators

Scalability of silicon-based phase-change oscillators is investigated through experimental and computational studies. These relaxation oscillators are composed of a small volume of silicon, dc biased through a load resistor and a capacitor, which melts due to self-heating and resolidifies upon discharge of the load capacitor. These phase changes lead to high-amplitude current spikes with oscillation frequency that scales with supply voltage, RC time constant, power delivery condition, and heating and cooling rates of the wire. Experimental results are obtained from structures fabricated using silicon-on-insulator substrates. Scaling effects of various parameters are explored using 3-D finite-element simulations coupled with SPICE models.

Upside-down FETS

To address key challenges in transistor scaling [1,2], we have used 3D oxide bonding technology in a new way, to fabricate CMOS devices and circuits in which the gate is on the opposite side of the channel from the contacts between the FET and the first wiring level (Ml).

Laterally-scaled Si/SiGe n-MODFETs with in situ and ion-implanted p-well doping

In order to fulfill their potential for enhanced performance, MODFETs must be scaled, both laterally and vertically. However, lateral scaling is particularly challenging because well and/or halo doping can lead to dopant incorporation in the 2D channel which can significantly degrade the mobility. Recently, we have demonstrated a technique for growing Si/SiGe n-MODFET layer structures with buried p-well doping while retaining an undoped channel region. In this paper, we describe the operation of laterally-scaled Si/SiGe n-MODFETs with buried in situ and ion-implanted p-well doping. We show that the devices have improved subthreshold behavior, greatly improved self-gain and improved speed-power product compared with undoped controls.

Timing high-speed microprocessor circuits using picosecond imaging circuit analysis

IBM Research has developed a time resolved imaging technique, Picosecond Imaging Circuit Analysis (PICA), which uses single photon events to analyze signals in modern microprocessors on a picosecond time scale. This paper will describe the experimental setup as well as the data management software. A case study of a particularly hard debug problem on a state of the art microprocessor will demonstrate the application of the PICA method.