K. G. Sharma

Design and analysis of low power 1-bit full adder cell

In this paper low power full adder using 11 transistors has been proposed. The main idea of design is based on improving the performance of 10 transistor full adder design mentioned in literature by sacrificing a transistor count. While the proposed circuit has negligible area overhead, it has remarkably improved power consumption and temperature sustainability when compared with existing design. BSIM3v3 90nm standard models are used for simulations on Tanner EDA tool.

High performance full adder cell: A comparative analysis

Full adder is an essential component for the design and development of all types of processors viz. digital signal processors (DSP), microprocessors etc. Adders are the core element of complex arithmetic operations like addition, multiplication, division, exponentiation etc. In most of these systems adder lies in the critical path that affects the overall speed of the system. So enhancing the performance of the 1-bit full adder cell is a significant goal. The present study proposes an energy efficient full adder cell with least MOS transistor count that reduces the serious problem of threshold loss. It considerably increases the speed. Result shows 45% improvement in threshold loss problem, 40% improvement in power-delay product over the other types of adders with comparable performance. The simulation has been carried out on Tanner EDA tool on BSIM3v3 90nm and 130nm technologies.

Modified SET D-Flip Flop Design for Low-Power VLSI Applications

Low power device design is now a vital field of research due to increase in demand of portable devices. This research paper proposes the modified Single Edge Triggered (SET) D-flip flop design for the portable applications. Design is tested for various substrate bias voltages in sub-threshold region to opt for better design. Design comparison between previously reported design and modified design is performed at 65nm and 45nm to show technology independence. Comparative simulation results show that area and power efficient SET D-FF design is better choice for portable applications.

PMOS based 1-Bit Full Adder Cell

This paper presents post layout simulations of a new 8T full adder cell using a new 3T XOR gate implemented by pMOS transistors only. This proposed design operates efficiently in super threshold region to achieve ultra low power and hence reduced power-delay product (PDP). The proposed design demonstrates its superiority against existing adder in terms of power–delay product, temperature sustainability and noise immunity. It also shows remarkable improvement in threshold loss as compared to existing 8T full adder for certain input combinations. Therefore, the proposed design outperforms the existing adder and proves to be an optimal option for low power and energy efficient applications. All the post-layout simulations have been performed at 45nm technology on Tanner EDA tool version 13.0.

Efficient design for transistor level and function

This paper proposes a new design of 2T AND gate. All the designs are compared with respect to the transistor count, power consumption, temperature sustain ability, noise immunity and parasitic capacitance in order to prove the superiority of proposed design over existing designs. The pre layout simulation has been carried out on BSIM3v3 90nm technology and post layout simulation has been performed on 0.5submicron technology using Tanner EDA tool.

SET D-flip flop design for portable applications

Increasing demand of portable devices creating larger scope in the field of Low power device design. VLSI designing of the efficient circuits is aiming towards the devices consuming less power and produces less delay with capability to operate in wider range of frequencies. This research paper proposes the modified Single Edge Triggered (SET) D-flip flop design for the low power applications. The earlier proposed design is tested for various substrate bias techniques in sub-threshold region to opt for better design. The overall area of the design is optimized to increase the chip density. Design comparison is performed at 65nm and 45nm to show the technology independence. Comparative simulation results show that area and power efficient SET D-FF design is better choice for portable applications.

2-Bit magnitude comparator using GDI technique

In recent years, low power design has become one of the prime focuses for the digital VLSI circuit. Keeping the same in mind a new design of 2-Bit GDI based Magnitude Comparator has been proposed and implemented with the help of full adder which is the basic building block of ALU. Proposed GDI technique based magnitude comparator has an advantage of less power consumption with respect to various design parameters; less on-chip area covered as less number of transistors are required in circuit design as compared to conventional CMOS magnitude comparator. Both the circuits are designed and simulated using Tanner EDA Tool version 12.6 at 45nm process technology.

High Performance Latch Design for Portable Application

In recent years, low power design has become one of the main focuses of digital VLSI circuits. As technology scales, leakage currents in contemporary CMOS logic have become one of the main power consumers. Contrary to conventional methods for power reduction, where efforts are taken to reduce subthreshold leakage, operation of digital circuits in the subthreshold region utilizes this current to minimize power consumption in low-frequency systems. This research paper proposes novel design of 8-transistor latch. The design performance is evaluated by comparing it with the conventional design of the latch. The simulation results are analyzed at 65nm and 45nm technology to show the technology independence of the design. The proposed design of latch is better suitable for the low power VLSI applications. KeywordsLevel converting Flip Flop, Portable Applications, Latch, Sub-threshold Region, Low Power applications.

A Novel Latch design for Low Power Applications

Low power device design is now a vital field of research due to increase in demand of portable devices. This research paper proposes novel design of 8-transistor latch. Design comparison with the conventional design is performed at 65nm and 45nm to show technology independence. Comparative simulation results show that area and power efficient latch design is better choice for portable applications.

Double Gate MOSFET circuit design

This paper presents a study of Double Gate MOSFET. The design possibilities of the Double Gate MOSFET will be explored in this paper which operates efficiently in sub threshold region to achieve ultra-low power and increases the performance of the circuit. The main objective of this paper is to understand the structure of Double Gate MOSFET while comparing them with traditional bulk MOSFET. The aim is to carry out simulations of Double Gate MOSFET and to improve the performance of MOSFET by studying the MOSFETs with double gate. Power consumption of the designed logic gates with Single Gate MOSFET and Double Gate MOSFET have been compared in this paper. Simulations are performed on SPICE tool at 45nm technology for a variety of inputs at different supply voltages and frequencies.