Tripti Sharma

PMOS based 1-Bit Full Adder Cell

This paper presents post layout simulations of a new 8T full adder cell using a new 3T XOR gate implemented by pMOS transistors only. This proposed design operates efficiently in super threshold region to achieve ultra low power and hence reduced power-delay product (PDP). The proposed design demonstrates its superiority against existing adder in terms of power–delay product, temperature sustainability and noise immunity. It also shows remarkable improvement in threshold loss as compared to existing 8T full adder for certain input combinations. Therefore, the proposed design outperforms the existing adder and proves to be an optimal option for low power and energy efficient applications. All the post-layout simulations have been performed at 45nm technology on Tanner EDA tool version 13.0.

2-Bit magnitude comparator using GDI technique

In recent years, low power design has become one of the prime focuses for the digital VLSI circuit. Keeping the same in mind a new design of 2-Bit GDI based Magnitude Comparator has been proposed and implemented with the help of full adder which is the basic building block of ALU. Proposed GDI technique based magnitude comparator has an advantage of less power consumption with respect to various design parameters; less on-chip area covered as less number of transistors are required in circuit design as compared to conventional CMOS magnitude comparator. Both the circuits are designed and simulated using Tanner EDA Tool version 12.6 at 45nm process technology.

9T full adder design in subthreshold region

This paper presents prelayout simulations of two existing 9T and new proposed 9T full adder circuit in subthreshold region to employ in ultralow-power applications. The proposed circuit consists of a new logic which is used to implement Sum module. The proposed design remarkably reduces power-delay product (PDP) and improves temperature sustainability when compared with existing 9T adders. Therefore, in a nut shell proposed adder cell outperforms the existing adders in subthreshold region and proves to be a viable option for ultralow-power and energy-efficient applications. All simulations are performed on 45nm standard model on Tanner EDA tool version 13.0.

Low Power Magnitude Comparator Circuit Design

paper presents a new low power 2-Bit magnitude comparator using full adder technique. The proposed magnitude comparator (PTL logic) has been compared with existing magnitude comparator (GDI technique). The performance analysis of both magnitude comparators is done on basis of power consumption with respect to input voltage, temperature, and frequency; using Tanner EDA tool version 12.6 at 45nm technology. The simulation results of proposed magnitude have shown remarkable performance in terms of power consumption, area and threshold loss in comparison to existing magnitude comparator. Thus proposed magnitude comparator can be viable option for low power application. Keywordscomparator, PTL logic, GDI technique, full adder and Low power.

Low Power 1-Bit 9T Full Adder Cell using XNOR Logic

In this paper a new low power and high performance 9T adder circuit using XNOR gate architecture is proposed which improves the performance of existing 8T adder by sacrificing the MOS transistor count by one. Simulation results demonstrate the superiority of the proposed adder against existing 8T adder in terms of power consumption and temperature sustainability. The combination of low power and better temperature sustainability makes the proposed full adder an optimal option for low power and energy efficient design. All simulations are performed on 90nm standard model on Tanner EDA tool version 13.0. Keywords—8T, 9T, XNOR gate, full adder and low power.

Analysis of Non Simultaneous Sybil Attack on DSR

is one of the most challenging issues in Mobile ad- hoc networks (MANETs). Most of the routing protocols in MANETs do not have an inbuilt mechanism to fight security attacks. Sybil attack is one such attack in which a single physical device takes on multiple identities in network thus behaving as multiple independent devices. With the help of these forged identities, the attacker can draw more benefits from the network by asking for more resources with the help of the multiple fake identities. The paper analyses the impact of Non-Simultaneous Sybil Attack on Dynamic Source Routing protocol (DSR). Its effect has been studied on performance metrics - End to End Delay and Throughput.

Low Power 3T XOR Cell using IDDG MOSFET

In this paper, a new design of three transistor XOR gate is proposed using Independent Driven Double Gate MOSFET to achieve ultra-low power in sub threshold conduction. The proposed design has been compared with the three transistor XOR implemented using Symmetrical Driven Double Gate MOSFET in sub threshold region. A three transistor XOR gate designed using Independent Driven Double Gate MOSFET is showing improved results in terms of power consumption with varying input voltage, temperature and operating frequencies. The simulation has been carried out on SPICE tool at 45 nm technology.

High Performance and Function Design on the Transistor Level

paper proposes a new design of pass transistor logic based 2T AND gate. Performance comparison of proposed gate with traditional CMOS, complementary pass-transistor logic design and GDI techniques is presented. Different methods have been compared with respect to the number of devices, power-delay product, temperature sustainability and noise immunity in order to prove the superiority of proposed design over existing ones. The simulation has been carried out on Tanner EDA tool on BSIM3v3 90nm technology. Keywordsgate, PTL and Power-delay product.

Energy Optimal Path Algorithm for routing in Static Adhoc Network using Greedy Approach (EOGR)

Wireless adhoc networks are excellent area for researchers with an algorithm background. In this paper we have given an algorithmic approach to the problem of routing with minimum energy consumption by the ad hoc network. we have proposed an energy optimal path algorithm used for routing in static adhoc networks using greedy approach of algorithm design. We have given the mathematical proof of correctness of proposed algorithm. We also performed simulation to show the effectiveness & correctness of our algorithm. Simulation results show that the proposed algorithm perform well in comparison to the GPSR algorithm in terms of energy, throughput & other factors.