Michel Ranjit Frei

Minimizing thermal resistance and collector-to-substrate capacitance in SiGe BiCMOS on SOI

We describe a low fabrication cost, high-performance implementation of SiGe BiCMOS on SOL The use of high-energy implant allows the simultaneous formation of the subcollector and an additional n-type region below the buried oxide. The combination of buried oxide layer and floating n-type region underneath results in a very low collector-to-substrate capacitance. We also show that this process option achieves a much lower thermal resistance than using SOI with deep trench isolation, both reducing cost and curbing self-heating effects.

Distributed effects in high power RF LDMOS transistors

This paper focuses on the effects of distributed RF transmission lines on performance aspects, such as, gain, output power, efficiency etc. in high power RF LDMOS amplifiers. The methodology to model and capture the distributed effects is discussed. Suitable alternatives to mitigate power loss due to distributive effects in large transistors are presented. Also, the contributions of the package to the overall device performance are addressed.

Design, test, and simulation of self-assembled micromachined rf inductors

Inductors are essential for fully integrated, complex RF circuits such as single chip radios. Both high Q, Q > 15, and high precision, +/- 2 percent, inductors are needed to meet phase noise specifications for on-chip VCOs and for reactive impedance matching to improve power transfer and linearity. We describe the design, test and simulation of self-assembled, micromachined inductors lifted away from the substrate by tensile stress in the metallization. The air gap reduces the capacitive coupling to the substrate, increasing both the Q and self-resonant frequency. For 2nH inductors we have measured Q-14 at 2GHz, with process variation < 2 percent. Increased temperature and current strongly increase the loss, but do not effect the inductance. The inductors are also relatively insensitive to mechanical excitation, with forces approximately 30gs required to significantly modulate the inductor loss under resonant excitation. Extensive EM simulations of this design methodology suggest that we should be able to reach Q > 25 at 2GHz and maintain 10GHz. We also compare these results with state of the art fully integrated Si RFIC planar inductors.

An approach for fabricating high performance inductors on low resistivity substrates

Porous Si layers up to 250 /spl mu/m in thickness are used to isolate spiral inductors from low resistivity substrates. Wafer curvature and SIMS analysis are done to address the manufacturability issue of porous Si. Spiral inductors with a single level Al on 2-inch, p-type substrates of 0.008 /spl Omega/-cm resistivity are demonstrated with Q=5.0 at 1.8 GHz for an L of 9 nH. Large inductors with L/spl sim/150 nH have been shown with the first resonance frequency at 1 GHz. The expected performance potential as well as factors that could be limiting the Q are discussed.

Modeling high power RF LDMOS amplifiers

This paper focuses on the package model extraction methodology and large signal model verification of high power RF LDMOS amplifiers. Results validating the extracted package models are presented. Accurate models of the power amplifier that also allow for simulations of the linearity aspects, such as IMD3 and IMD5 is presented. Comparisons between measured and modeled data is presented to validate the package models.