K. O. Kenneth

Fully integrated 5.35-GHz CMOS VCOs and prescalers

Two 5.35-GHz monolithic voltage-controlled oscillators (VCOs) and two prescalers have been fabricated in a digital 0.25-/spl mu/m CMOS process. One VCO uses p/sup +//n-well diodes, while the other uses MOS varactors, Q of 57 at 5.5 GHz and 0 V bias (low-Q condition) for a p/sup +//n-well varactor has been achieved. For an MOS varactor, it is possible to achieve a quality factor of 140 at 5.5 GHz. The tuning ranges of the VCOs are >310 MHz, and their phase noise is <-116.5 dBc/Hz at a 1-MHz offset while consuming /spl sim/7 mW power at V/sub DD/=1.5 V. The low phase noise is achieved by using only PMOS transistors in the VCO core and by optimizing the resonator layout. The prescalers utilize a variation of the source-coupled logic. The power consumption is 4.1 mW at 1.5-V V/sub DD/ and 5.4 GHz. By widening the transistors in the first three divide-by-two stages, the maximum operating frequency is increased to 9.96 GHz at V/sub DD/=2.5 V.

Demonstration of a switched resonator concept in a dual-band monolithic CMOS LC-tuned VCO

A switched resonator concept which allows better trade-off between phase noise and power consumption is demonstrated using a dual band VCO. The dual-band VCO operates near 900 MHz and 1.8 GHz with phase noise of -125 and 123 dBc/Hz at a 600-KHz offset and 16-mW power consumption. Compared to a single band 1.8 GHz VCO, the dual-band VCO has almost the same phase noise and power consumption.

Progress and Challenges Towards Terahertz CMOS Integrated Circuits

Key components of systems operating at high millimeter wave and sub-millimeter wave/terahertz frequencies, a 140-GHz fundamental mode voltage controlled oscillator (VCO) in 90-nm CMOS, a 410-GHz push-push VCO with an on-chip patch antenna in 45-nm CMOS, and a 125-GHz Schottky diode frequency doubler, a 50-GHz phase-locked loop with a frequency doubled output at 100 GHz, a 180-GHz Schottky diode detector and a 700-GHz plasma wave detector in 130-nm CMOS are demonstrated. Based on these, and the performance trends of nMOS transistors and Schottky diodes fabricated in CMOS, paths to terahertz CMOS circuits and systems including key challenges that must be addressed are suggested. The terahertz CMOS is a new opportunity for the silicon integrated circuits community.

Active Terahertz Imaging Using Schottky Diodes in CMOS: Array and 860-GHz Pixel

Schottky-barrier diodes (SBDs) fabricated in CMOS without process modification are shown to be suitable for active THz imaging applications. Using a compact passive-pixel array architecture, a fully-integrated 280-GHz 4 × 4 imager is demonstrated. At 1-MHz input modulation frequency, the measured peak responsivity is 5.1 kV/W with ±20% variation among the pixels. The measured minimum NEP is 29 pW/Hz1/2. Additionally, an 860-GHz SBD detector is implemented by reducing the number of unit cells in the diode, and by exploiting the efficiency improvement of patch antenna with frequency. The measured NEP is 42 pW/Hz1/2 at 1-MHz modulation frequency. This is competitive to the best reported performance of MOSFET-based pixel measured without attaching an external silicon lens (66 pW/Hz1/2 at 1 THz and 40 pW/Hz1/2 at 650 GHz). Given that incorporating the 280-GHz detector into an array increased the NEP by ~ 20%, the 860-GHz imager array should also have the similar NEP as that for an individual detector. The circuits were utilized in a setup that requires neither mirrors nor lenses to form THz images. These suggest that an affordable and portable fully-integrated CMOS THz imager is possible.

A 21-GHz 8-Modulus Prescaler and a 20-GHz Phase-Locked Loop Fabricated in 130-nm CMOS

A 1.5-V 256-263 8-modulus prescaler and a 1.5-V integer-N phase-locked loop (PLL) with eight different output frequencies have been implemented in a 0.13-mum foundry CMOS process. The synchronous divide-by-4/5 circuit uses current mode logic (CML) D-flip-flops with resistive loads to achieve 21-GHz maximum operating frequency at input power of 0 dBm. The divider is used to implement an 8-modulus prescaler consuming 6-mA current and 9-mW power. This extremely low power consumption is achieved by radically decreasing the sizes of transistors in the divider. Utilizing the prescaler, a charge-pump integer-N PLL has been demonstrated with 20-GHz output frequency. The in-band phase noise of the PLL at 60-kHz offset and out-of-band phase noise at 10-MHz offset are ~-80 dBc/Hz and -116.1 dBc/Hz, respectively. The locking range is from 20.05 to 21 GHz. The PLL consumes 15-mA current and 22.5-mW power from a 1.5-V power supply.

A 31.3-dBm Bulk CMOS T/R Switch Using Stacked Transistors With Sub-Design-Rule Channel Length in Floated p-Wells

A 31.3-dBm 900-MHz bulk CMOS T/R switch with transmit (TX) and receive (RX) insertion losses of 0.5 and 1.0 dB and isolation of 29 dB is demonstrated. The switch utilizes a floating-body technique, feed-forward capacitors, and 3-stack 3.3-V MOSFETs with 0.26-mum sub-design-rule (SDR) channel length. Using these, a 28-dBm 2.4-GHz T/R switch with TX and RX insertion losses of 0.8 and 1.2 dB, and isolation of 24 dB is also demonstrated. The power handling capability is limited by an abrupt output power drop before reaching the normal 1-dB compression point. The circuits are implemented in the UMC 130-nm mixed-mode triple-well CMOS process.

125-GHz Diode Frequency Doubler in 0.13-

The first mm-wave Schottky diode frequency doubler fabricated in CMOS is demonstrated. The doubler built in 130-nm CMOS uses a balanced topology with two shunt Schottky barrier diodes, and exhibits ~ 10-dB conversion loss as well as -1.5-dBm output power at 125 GHz. The input matching is better than -10&nbsp;dB from 61 to 66 GHz. The rejection of fundamental signal at output is greater than 12 dB for input frequency from 61 to 66&nbsp;GHz. The doubler can generate signals up to 140 GHz.

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A 900-MHz single-stage low noise amplifier (LNA), requiring one external inductor and matched to 50-/spl Omega/ at both the input and output, has been implemented in a standard digital 0.8-/spl mu/m CMOS technology. Measured noise figures for the LNA in package are 2 dB at 6.2 mW, 1.78 dB at 8.1 mW, 1.5 dB at 13.2 mW, and 1.2 dB at 30 mW. At 30 mW and V/sub DD/=3.0 V, the LNA has a power gain of 14.5 dB, and an IIP3 of -1 dBm. At 6.2 mW and V/sub DD/=2.7 V, the LNA has a power gain of 9.4 dB, and an IIP3 of -3.8 dBm.

CMOS

A wireless interconnect system for clock distribution which transmits and receives microwave signals across a chip using integrated antennas, receivers, and transmitters is presented. All of the com-ponents of the system are demonstrated at 15 GHz in a 0.18-m CMOS technology. Wireless interconnection is achieved over a distance of 5.6 mm.

A 900-MHz, 0.8-/spl mu/m CMOS low noise amplifier with 1.2-dB noise figure

The impact of on-chip metal interference structures, such as a power grid, local clock trees and data lines, on on-chip antenna performance has been investigated. A power grid significantly changes the input impedance and the phase of S/sub 12/ for an antenna pair, and reduces |S/sub 12/|. However, the addition of extra metal structures in the presence of a power grid has a much attenuated impact on the antenna characteristics. The reduction in |S/sub 12/| can be traded for increased predictability of antenna performance. Exploiting this observation, a set of design rules for increasing the predictability of on-chip antenna characteristics is proposed.