K.P. MacWilliams

Enhancement-mode quantum-well Ge/sub x/Si/sub 1-x /PMOS

The authors demonstrate the feasibility of a p-channel quantum-well MOSFET on a Ge/sub x/Si/sub 1-x//Si heterostructure. The advantages of the enhancement-mode p-channel MOSFET device compared to GeSi MODFETs are its high impedance, channel mobility, and channel transconductance. The device shows good saturation and cutoff behaviour. A saturation transconductance of 64 mS/mm was measured for a 0.7- mu m channel device at a drain-to-source voltage of -2.5 V. The channel mobility was found to be higher than that of a similarly processed Si p-channel MOSFET.<<ETX>>

High‐mobility p‐channel metal‐oxide‐semiconductor field‐effect transistor on strained Si

An enhancement‐mode p‐channel metal‐oxide‐semiconductor field‐effect transistor (PMOSFET) is fabricated on a strained Si layer for the first time. A biaxial strain in a thin Si layer is produced by pseudomorphically growing this layer on a Ge0.25Si0.75 buffer layer which is grown on a Si substrate. At higher magnitude of gate bias, channel mobility of a strained Si PMOSFET has been found to be 50% higher than that of an identically processed conventional Si PMOSFET.

High-mobility GeSi PMOS on SIMOX

A new p-channel GeSi-SIMOX device is presented. The device consists of a Si/Ge/sub 0.3/Si/sub 0.7//Si channel, which is grown pseudomorphically on a SIMOX substrate. Due to reduced vertical electric field and band bending at the surface of a GeSi-SIMOX device, hole confinement in the buried channel is improved over that of a GeSi-bulk device. Experimentally, the effective channel mobility of this device is found to be 90% higher than that of an identically processed conventional SIMOX device.<<ETX>>

Quantifying ESD/EOS latent damage and integrated circuit leakage currents

The correlation of IC leakage current with ESD/EOS latent damage is studied. Quantification of latent damage as a function of leakage current is determined for the two primary ESD/EOS latent damage mechanisms. This relationship explicitly shows the reduction in lifetime with ESD/EOS damage (type dependent) and also offers the possibility for a simple screening procedure for latent damage.

Hole confinement in a Si/GeSi/Si quantum well on SIMOX

In this work, hole confinement in a MBE-grown Si/GeSi/Si quantum well on SIMOX substrate is investigated in detail using device simulation, electronic measurements, and optical techniques. The hole confinement is clearly demonstrated from GeSi PMOSFET measurements. The experimental results are in good agreement with device simulation results. The quantum confinement of holes in the GeSi quantum well on SIMOX is confirmed using photoluminescence measurements.

Dependence of LDD device optimization on stressing parameters at 77 K

The optimization of lightly doped drain (LDD) devices to minimize hot-carrier-induced device degradation at cryogenic temperature is studied. The degradation behavior of LDD devices at 77 K does not follow the simple behavior modeled by substrate current (I/sub sub/). Also, for a given device, the maximum degradation is not observed at the maximum I/sub sub/ gate bias. Furthermore, the optimum LDD design is found to depend on the specific stressing bias conditions at 77 K. Therefore, the conventional DC acceleration technique cannot predict operating device lifetime or the optimum cryogenic LDD design.<<ETX>>

One-micrometer, radiation-hardened complementary metal oxide semiconductor for cryogenic analog applications

Results are presented of a process-development effort to achieve a 1-Mrad silicon (Si) radiation-hardening capability at temperatures down to 40 K, using Texas Instruments high volume, 1-micrometer commercial process. The one-micrometer process was characterized at 77 K and 40 K: radiation effects on the baseline SiO2 gate dielectric and N-channel field effect transistor edges were observed, as were freeze-out and hot-carrier effects of the lightly doped drain implants. These freeze-out phenomena were confirmed, using SUPREM, MINIMOS, and MEDICI. The simulated data compared favorably with measured results. Simulations were run, using various implant doses and profiles to eliminate the freeze-out and hot-carrier effects in the new process. Devices having these simulated profiles were processed, and the results are presented.

The effects of hydrogen and deuterium incorporation on the electrical performance of a GaAs MESFET

A commercial GaAs MESFET annealed in 5% hydrogen showed shifts in its turn-on voltage and degradation in both its transconductance and drain current. Annealing in deuterium showed similar, though less extensive behavior, indicating that deuterium diffuses into the devices slower than hydrogen. A thin film diffusion experiment showed that the incorporation of hydrogen into the gate area is greatest when platinum is exposed to the hydrogen. Provides supporting evidence that diffusion of hydrogen occurs at the Pt sidewalls and not at the Au surface of the Au/Pt/Ti gate metal.

PMOS hot-carrier rebound and degradation

Previously, in detailed characterization of the NMOS cryogenic hot-carrier failure mode, major deviations from room temperature behavior were found. However, to date, no similar detailed analysis of the PMOS cryogenic hot-carrier effect has been performed. The purpose of this work is to investigate the PMOS hot carrier effect at cryogenic temperatures. One of our primary findings shows that PMOS devices aged at low temperatures can undergo a drastic rebound-like effect that results in distinct reduction in device drive and large threshold voltage shift. PMOS degradation of this degree is not observed for room temperature hot-carrier aging. Charge pumping measurements are used to measure the different behaviors with 77 K and 300 K hot-carrier stressing. Although the initial damage appears similar (same gm increase and Vt shift with stress time), subsequent annealing indicates that the damage mechanism at 77 K differs markedly from that at 300 K. Low temperature stressing initially induces the typical room temperature gm increase due to channel length shortening caused by trapped electrons. However, low-temperature stressing also appears to induce hole generation and substantial interface state creation unlike 300 K stressed devices. This finding may have serious reliability implications for PMOS devices operated at cryogenic temperatures.<<ETX>>

Temperature dependence of hot-carrier lifetime due to trapped charge and interface state generation

Hot carrier device lifetime diminishes dramatically as operating temperature decreases. The hot carrier lifetime at liquid nitrogen temperature is usually several orders of magnitude lower than at room temperature. In this work, we show the dependence of hot carrier device lifetime of LDD nMOSFETs on temperature and stress condition in the temperature range from 78 K to room temperature. There is a cross-over point at which the worst-case hot carrier stress condition switches from Vg approximately equals 1/2 Vd (Vg Ibmax) to Vg equals Vd with decreasing temperature. Consequently, the dominant damage mechanism switches from interface state generation to trapped charge generation.