Jason C. S. Woo

The impact of high-/spl kappa/ gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs

The potential impact of high-/spl kappa/ gate dielectrics on device short-channel performance is studied over a wide range of dielectric permittivities using a two-dimensional (2-D) simulator implemented with quantum mechanical models. It is found that the short-channel performance degradation is caused by the fringing fields from the gate to the source/drain regions. These fringing fields in the source/drain regions further induce electric fields from the source/drain to channel which weakens the gate control. The gate dielectric thickness-to-length aspect ratio is a proper parameter to quantify the percentage of the fringing field and thus the short channel performance degradation. In addition, the gate stack architecture plays an important role in the determination of the device short-channel performance degradation. Using double-layer gate stack structures and low-/spl kappa/ dielectric as spacer materials can well confine the electric fields within the channel thereby minimizing short-channel performance degradation. The introduction of a metal gate not only eliminates the poly gate depletion effect, but also improves short-channel performance. Several approaches have been proposed to adjust the proper threshold voltage when midgap materials or metal gates are used.

A MEMS based amperometric detector for E-Coli bacteria using self-assembled monolayers

We developed a system for amperometric detection of Escherichia coli (E. coli) based on the integration of microelectromechanical systems (MEMS), self-assembled monolayers (SAMS), DNA hybridization, and enzyme amplification. Using MEMS technology, a detector array was fabricated which has multiple electrodes deposited on a Si wafer and was fully reusable. Using SAMs, a monolayer of the protein streptavidin was immobilized on the working electrode (Au) surface to capture rRNA from E. coli. Three different approaches can be used to immobilize streptavidin onto Au, direct adsorption of the protein on bare Au, binding the protein to a biotinylated thiol SAM on Au, and binding the protein to a biotinylated disulfide monolayer on Au. The biotinylated thiol approach yielded the best results. High specificity for E. coli was achieved using ssDNA-rRNA hybridization and high sensitivity was achieved using enzymatic amplification with peroxidase as the enzyme. The analysis protocol can be conducted with solution volumes on the order of a few microliters and completed in 40 min. The detection system was capable of detecting 1000 E. coli cells without polymerase chain reaction with high specificity for E. coli vs. the bacteria Bordetella bronchiseptica.

The Tunnel Source (PNPN) n-MOSFET: A Novel High Performance Transistor

As MOSFET is scaled below 90 nm, many daunting challenges arise. Short-channel effects (SCEs; drain-induced barrier lowering and VTHmiddotrolloff), off-state leakage, parasitic capacitance, and resistance severely limit the performance of these transistors. New device innovations are essential to overcome these difficulties. In this paper, we propose the concept of a novel tunnel source (PNPN) n-MOSFET based on the principle of band-to- band tunneling. It is found that the PNPN n-MOSFET has the potential of steep subthreshold swing and improved Ion in addition to immunities against SCEs. Therefore, such a PNPN n-MOSFET can overcome the ever-degrading on-off characteristics of the deeply scaled conventional MOSFET. The design of the PNPN n-MOSFET was extensively examined using simulations. Devices with source-side tunneling junctions were fabricated on bulk substrates using spike anneal, and the experimental data is presented.

Enhancement-mode quantum-well Ge/sub x/Si/sub 1-x /PMOS

The authors demonstrate the feasibility of a p-channel quantum-well MOSFET on a Ge/sub x/Si/sub 1-x//Si heterostructure. The advantages of the enhancement-mode p-channel MOSFET device compared to GeSi MODFETs are its high impedance, channel mobility, and channel transconductance. The device shows good saturation and cutoff behaviour. A saturation transconductance of 64 mS/mm was measured for a 0.7- mu m channel device at a drain-to-source voltage of -2.5 V. The channel mobility was found to be higher than that of a similarly processed Si p-channel MOSFET.<<ETX>>

High-gain lateral bipolar action in a MOSFET structure

A hybrid-mode device based on a standard submicrometer CMOS technology is presented. The device is essentially a MOSFET in which the gate and the well are internally connected to form the base of a lateral bipolar junction transistor (BJT). At low collector current levels, lateral bipolar action with a current gain higher than 1000 is achieved. No additional processing steps are needed to obtain the BJT when the MOSFET is properly designed. n-p-n BJTs with a 0.25- mu m base width have been successfully fabricated in a p-well 0.25- mu m bulk n-MOSFET process. The electrical characteristics of the n-MOSFET and the lateral n-p-n BJT at room and liquid nitrogen temperatures are reported. >

Salicidation process using NiSi and its device application

Self-aligned silicidation is a well-known process to reduce source, drain, and gate resistances of submicron metal-oxide-semiconductor devices. This process is particularly useful for devices built on very thin Si layers (∼1000 A or less) on insulators because of the large source and drain resistances associated with the thin Si layer. NiSi is a good candidate for salicidation process due to its low resistivity, low formation temperature, little silicon consumption, and large stable processing temperature window. In this article, the formation of nickel mono-silicide (NiSi) using rapid thermal annealing, the thermal stability of NiSi on n+ poly-Si and the contact resistance of NiSi on n+ Si layers in a SIMOX structure were investigated. NiSi salicidation process was, then, incorporated into a NMOS/SIMOX device fabrication for partial and full consumption of the Si in the source and drain regions during the salicidation process. The effects of void formation and silicide encroachment on the device performa...

Lifetime of photogenerated carriers in silicon-on-insulator rib waveguides

The lifetime of photogenerated carriers in silicon-on-insulator rib waveguides is studied in connection with the optical loss they produce via nonlinear absorption. We present an analytical model as well as two-dimensional numerical simulation of carrier transport to elucidate the dependence of the carrier density on the geometrical features of the waveguide. The results suggest that effective carrier lifetimes of ⩽1ns can be obtained in submicron waveguides resulting in negligible nonlinear absorption. It is also shown that the lifetime and, hence, carrier density can be further reduced by application of a reverse bias pn junction.

High‐mobility p‐channel metal‐oxide‐semiconductor field‐effect transistor on strained Si

An enhancement‐mode p‐channel metal‐oxide‐semiconductor field‐effect transistor (PMOSFET) is fabricated on a strained Si layer for the first time. A biaxial strain in a thin Si layer is produced by pseudomorphically growing this layer on a Ge0.25Si0.75 buffer layer which is grown on a Si substrate. At higher magnitude of gate bias, channel mobility of a strained Si PMOSFET has been found to be 50% higher than that of an identically processed conventional Si PMOSFET.

Wet oxidation of GeSi strained layers by rapid thermal processing

A cold‐wall rapid thermal processor is used for the wet oxidation of the commensurately grown GexSi1−x layers on Si substrates. The rate of oxidation of the GexSi1−x layer is found to be significantly higher than that of pure Si, and the oxidation rate increases with the increase in the Ge content in GexSi1−x layer. The oxidation rate of GexSi1−x appears to decrease with increasing oxidation time for the time‐temperature cycles considered here. Employing high‐frequency and quasi‐static capacitance‐voltage measurements, it is found that a fixed negative oxide charge density in the range of 1011– 1012/cm2 and the interface trap level density (in the mid‐gap region) of about 1012/cm2 eV are present. Further, the density of this fixed interface charge at the SiO2/GeSi interface is found to increase with the Ge concentration in the commensurately grown GeSi layers.

Large Scale Pattern Graphene Electrode for High Performance in Transparent Organic Single Crystal Field-Effect Transistors

High quality, large grain size graphene on polycrystalline nickel film on two inch silicon wafers was successfully synthesized by the chemical vapor deposition (CVD) method. The polydimethylsiloxane (PDMS) stamping method was used for graphene transferring in this experiment. The graphene transferred onto Al2O3/ITO substrates was patterned into macroscopic dimension electrodes using conventional lithography followed by oxygen plasma etching. Experimental results show that this graphene can serve as transparent source and drain electrodes in high performance organic semiconductor nanoribbon organic field-effect transistors (OFETs), facilitating high hole injection efficiency due to the preferred work function match with the channel material: single crystalline copper phthalocyanine (CuPc) nanoribbons. The nanoribbons were grown on top of the patterned graphene via evaporate-deposition to form the FET device. The carrier mobility and on/off current ratio of such devices were measured to be as high as 0.36 cm2/(V s) and 10(4).