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Dive into the research topics where K. Poulose Jacob is active.

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Featured researches published by K. Poulose Jacob.


International Journal of Computer Science & Applications | 2015

Jerim-320: A New 320-Bit Hash Function Compared To Hash Functions With Parallel Branches

Sheena Mathew; K. Poulose Jacob

Augmented reality (AR) is a technology which provides real time integration of digital content with the information available in real world. Augmented reality enables direct access to implicit information attached with context in real time. Augmented reality enhances our perception of real world by enriching what we see, feel, and hear in the real environment. This paper gives comparative study of various augmented reality software development kits (SDK’s) available to create augmented reality apps. The paper describes how augmented reality is different from virtual reality; working of augmented reality system and different types of tracking used in AR.


southern conference programmable logic | 2009

Performance analysis of double digit decimal multiplier on various FPGA logic families

Rekha K. James; K. Poulose Jacob; Sreela Sasi

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that performs 2 digit multiplications simultaneously in one clock cycle. This design offers low latency and high throughput. When multiplying two n-digit operands to produce a 2n-digit product, the design has a latency of [(n/2 +1] cycles. The paper presents area and delay comparisons for 7-digit, 16-digit, 34-digit double digit decimal multipliers on different families of Xilinx, Altera, Actel and Quick Logic FPGAs. The multipliers presented can be extended to support decimal floating-point multiplication for IEEE P754 standard.


international conference on data science and engineering | 2012

Cooperative caching techniques for mobile ad hoc networks

Preetha Theresa Joy; K. Poulose Jacob

Data caching can remarkably improve the efficiency of information access in a wireless ad hoc network by reducing the access latency and bandwidth usage. The cache placement problem minimizes total data access cost in ad hoc networks with multiple data items. The ad hoc networks are multi hop networks without a central base station and are resource constrained in terms of channel bandwidth and battery power. By data caching the communication cost can be reduced in terms of bandwidth as well as battery energy. As the network node has limited memory the problem of cache placement is a vital issue. This paper attempts to study the existing cooperative caching techniques and their suitability in mobile ad hoc networks.


International Journal of Distributed and Parallel systems | 2012

A PROBABILISTIC APPROACH TO REDUCE THE ROUTE ESTABLISHMENT OVERHEAD IN AODV ALGORITHM FOR MANET

K G Preetha; A. Unnikrishnan; K. Poulose Jacob

Mobile Ad-hoc Networks (MANETS) is a collection of wireless nodes without any infrastructure support. The nodes in MANET can act as either router or source and the control of the network is distributed among nodes. The nodes in MANETS are highly mobile and it maintains dynamic interconnection between those mobile nodes. MANTEs have been considered as isolated stand-alone network. This can turn the dream of networking “at any time and at any where” into reality. The main purpose of this paper is to study the issues in route discovery process in AODV protocol for MANET. Flooding of route request message imposes major concern in route establishment. This paper suggests a new approach to reduce the routing overhead during the route discovery phase. By considering the previous behaviour of the network, the new protocol reduces the unwanted searches during route establishment process.


Archive | 2009

Reversible Binary Coded Decimal Adders using Toffoli Gates

Rekha K. James; K. Poulose Jacob; Sreela Sasi

Reversibility plays a fundamental role when computations with minimal energy dissipation are considered. This research describes Toffoli Gate (TG) implementations of conventional Binary Coded Decimal (BCD) adders, adders for Quick Addition of Decimals (QAD), and carry select BCD adders suitable for multi-digit addition. For an N-digit fast adder, partial parallel processing is done on all digits in the decimal domain. Such high-speed BCD adders find application in realtime processors and internet-based computing. An analysis of delay normalized to a TG and quantum cost of BCD adders is presented. Implementations using TGs and Fredkin Gates (FRGs) are compared based on quantum cost, number of gates, garbage count and delay, and the results are tabulated.


International Journal of Computer Applications | 2012

Discrete Wavelet Transforms and Artificial Neural Networks for Recognition of Isolated Spoken Words

Sonia Sunny; David Peter S; K. Poulose Jacob

recognition is a fascinating application of Digital Signal Processing and has many real-world applications. In this paper, a speech recognition system is developed for isolated spoken words using Discrete Wavelet Transforms (DWT) and Artificial Neural Networks (ANN). Speech signals are one-dimensional and are random in nature. Isolated words from Malayalam, one of the four major Dravidian languages of southern India are chosen for recognition. Daubechies wavelets are employed here. A multi- layer neural network trained with back propagation training algorithm is used for classification purpose. The proposed method is implemented for 50 speakers uttering 20 isolated words each. The experimental results show good recognition accuracy and the efficiency of combining these two techniques.


nature and biologically inspired computing | 2009

High performance, low latency double digit decimal multiplier on ASIC and FPGA

Rekha K. James; K. Poulose Jacob; Sreela Sasi

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that offers low latency and high throughput. This design performs two digit multiplications simultaneously in one clock cycle. Double digit fixed point decimal multipliers for 7digit, 16 digit and 34 digit are simulated using Leonardo Spectrum from Mentor Graphics Corporation using ASIC Library. The paper also presents area and delay comparisons for these fixed point multipliers on Xilinx, Altera, Actel and Quick logic FPGAs. This multiplier design can be extended to support decimal floating point multiplication for IEEE 754- 2008 standard.


2012 International Conference on Information Retrieval & Knowledge Management | 2012

Image retrieval using colour and texture features of Regions Of Interest

E. R. Vimina; K. Poulose Jacob

This paper proposes a region based image retrieval system using the local colour and texture features of image sub regions. The Regions Of Interest (ROI) are roughly identified by segmenting the image into fixed partitions, finding the edge map and filling the holes in edge map. The colour and texture features of the ROIs are computed from the histograms of the quantized HSV colour space and Gray Level Co-occurrence Matrix (GLCM) respectively. A combined colour and texture feature vector is computed for each ROI and Euclidean distance measure is used for computing the distance between the features of the query and target image. Preliminary experimental results show that the proposed method provides better retrieving result than some of the existing methods.


international conference on computing, communication and networking technologies | 2010

An adaptive cluster based routing scheme for mobile wireless sensor networks

G. Santhosh Kumar; A. Sitara; K. Poulose Jacob

Clustering schemes improve energy efficiency of wireless sensor networks. The inclusion of mobility as a new criterion for the cluster creation and maintenance adds new challenges for these clustering schemes. Cluster formation and cluster head selection is done on a stochastic basis for most of the algorithms. In this paper we introduce a cluster formation and routing algorithm based on a mobility factor. The proposed algorithm is compared with LEACH-M protocol based on metrics viz. number of cluster head transitions, average residual energy, number of alive nodes and number of messages lost.


ieee international conference on advanced infocomm technology | 2013

A location aided cooperative caching protocol for mobile ad hoc networks

Preetha Theresa Joy; K. Poulose Jacob

Cooperative caching is an attractive solution for reducing bandwidth demands and network latency in mobile ad hoc networks. Deploying caches in mobile nodes can reduce the overall traffic considerably. Cache hits eliminate the need to contact the data source frequently, which avoids additional network overhead. In this paper we propose a data discovery and cache management policy for cooperative caching, which reduces the caching overhead and delay by reducing the number of control messages flooded in to the network. A cache discovery process based on location of neighboring nodes is developed for this. The cache replacement policy we propose aims at increasing the cache hit ratio. The simulation results gives a promising result based on the metrics of studies.

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Dive into the K. Poulose Jacob's collaboration.

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Rekha K. James

Cochin University of Science and Technology

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E. R. Vimina

Cochin University of Science and Technology

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Preetha Theresa Joy

Cochin University of Science and Technology

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T.K. Shahana

Cochin University of Science and Technology

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A. Unnikrishnan

United Kingdom Ministry of Defence

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M H Supriya

Cochin University of Science and Technology

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Babita R. Jose

Cochin University of Science and Technology

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G. Santhosh Kumar

Cochin University of Science and Technology

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Peter S David

Cochin University of Science and Technology

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