Babita R. Jose

Performance analysis of FIR digital filter design: RNS versus traditional

This paper presents performance analysis of Residue Number System (RNS) based Finite Impulse Response (FIR) digital filters and traditional FIR filters. This research is motivated by the importance of an efficient filter implementation for digital signal processing. The comparison is done in terms of speed and area requirement for various filter specifications. RNS based FIR filters operate more than three times faster and consumes only about 60% of the area than traditional fitter when number of filter taps is more than 32. The area for RNS filter is increasing at a lesser rate than that for traditional resulting in low-power consumption. RNS is a non-weighted number system without carry propagation between different residue digits. This enables simultaneous parallel processing on all the digits resulting in high speed addition and multiplication in RNS domain. Such compact and high speed real-time digital filters find applications in radar, communications and image processing systems.

A Multi-Mode Sigma-Delta ADC for GSM/WCDMA/WLAN Applications

The demand for new telecommunication services requiring higher capacities, data rates and different operating modes have motivated the development of new generation multi-standard wireless transceivers. In multi-standard design, sigma-delta based ADC is one of the most popular choices. To this end, in this paper we present cascaded 2-2-2 reconfigurable sigma-delta modulator that can handle GSM, WCDMA and WLAN standards. The modulator makes use of a low-distortion swing suppression topology which is highly suitable for wide band applications. In GSM mode, only the first stage (2nd order ∑-Δ ADC) is used to achieve a peak SNDR of 88dB with over-sampling ratio of 160 for a bandwidth of 200KHz and for WCDMA mode a 2-2 cascaded structure (4th order) is turned on with 1-bit in the first stage and 2-bit in the second stage to achieve 74 dB peak SNDR with over-sampling ratio of 16 for a bandwidth of 2MHz. Finally, a 2-2-2 cascaded MASH architecture with 4-bit in the last stage is proposed to achieve a peak SNDR of 58dB for WLAN for a bandwidth of 20MHz. The novelty lies in the fact that unused blocks of second and third stages can be made inactive to achieve low power consumption. The modulator is designed in TSMC 0.18um CMOS technology and operates at 1.8 supply voltage.

RNS Based Programmable Multi-Mode Decimation Filter for WCDMA and WiMAX

The recent trends envisage multi-standard architectures as a promising solution for the future wireless transceivers to attain higher system capacities and data rates. The computationally intensive decimation filter plays an important role in channel selection for multi-mode systems. An efficient reconfigurable implementation is a key to achieve low power consumption. To this end, this paper presents a dual-mode Residue Number System (RNS) based decimation filter which can be programmed for WCDMA and 802.16e standards. Decimation is done using multistage, multirate finite impulse response (FIR) filters. These FIR filters implemented in RNS domain offers high speed because of its carry free operation on smaller residues in parallel channels. Also, the FIR filters exhibit programmability to a selected standard by reconfiguring the hardware architecture. The total area is increased only by 24% to include WiMAX compared to a single mode WCDMA transceiver. In each mode, the unused parts of the overall architecture is powered down and bypassed to attain power saving. The performance of the proposed decimation filter in terms of critical path delay and area are tabulated.

Spectrum Prediction in Cognitive Radio Networks: A Bayesian Approach

Spectrum sensing is an important activity in the Cognitive Radio (CR) scenario. Presence of primary users (PU) over a specific band has to be monitored periodically in each time slots. Spectrum sensing and data communication have to be completed in each time slot. If we can reduce the time required for spectrum sensing, more data can be transmitted in the specified time slot. If the presence of a PU can be predicted by a CR, throughput of the system can be improved. In this paper we define a simple approach based on Bayesian theorem to predict spectrum occupancy status of PU, from its spectrum occupancy pattern. Its performance is compared with exponential weighted moving average (EWMA) based approach to predict the spectrum occupancy information. A modification to EWMA is also suggested named hybrid approach by including the Bayesian probability within the above approach. Their performance is compared in terms of predicted probability and spectrum decision. Spectrum decision at different parameters of beta distribution is compared. Impact of number of previous data considered for prediction is also explored. Bit error rate of Bayesian approach is found less at certain data distributions. Computational requirement of Bayesian approach is also found relatively less.

GA-based optimization of a fourth-order sigma-delta modulator for WLAN

Over-sampling sigma-delta analogue-to-digital converters (ADCs) are one of the key building blocks of state of the art wireless transceivers. In the sigma-delta modulator design the scaling coefficients determine the overall signal-to-noise ratio. Therefore, selecting the optimum value of the coefficient is very important. To this end, this paper addresses the design of a fourth-order multi-bit sigma-delta modulator for wireless local area networks (WLAN) receiver with feed-forward path and the optimum coefficients are selected using genetic algorithm (GA)-based search method. In particular, the proposed converter makes use of low-distortion swing suppression SDM architecture which is highly suitable for low oversampling ratios to attain high linearity over a wide bandwidth. The focus of this paper is the identification of the best coefficients suitable for the proposed topology as well as the optimization of a set of system parameters in order to achieve the desired signal-to-noise ratio. GA-based search engine is a stochastic search method which can find the optimum solution within the given constraints.

Dual-mode RNS based programmable decimation filter for WCDMA and WLANa

The recent trends envisage multi-standard architectures as a promising solution for the future wireless transceivers. The computationally intensive decimation filter plays an important role in channel selection for multi-mode systems. An efficient reconfigurable implementation is a key to achieve low power consumption. To this end, this paper presents a dual-mode Residue Number System (RNS) based decimation filter which can be programmed for WCDMA and 802.11a standards. Decimation is done using multistage, multirate finite impulse response (FIR) filters. These FIR filters implemented in RNS domain offers high speed because of its carry free operation on smaller residues in parallel channels. Also, the FIR filters exhibit programmability to a selected standard by reconfiguring the hardware architecture. The total area is increased only by 33% to include WLANa compared to a single mode WCDMA transceiver. In each mode, the unused parts of the overall architecture is powered down and bypassed to attain power saving. The performance of the proposed decimation filter in terms of critical path delay and area are tabulated.

Design of Reversible Finite Field Arithmetic Circuits with Error Detection

Motivated by the potential of reversible computing, we present a systematic method for the designing reversible arithmetic circuits for finite field or Galois fields of form GF(2m). It is shown that an adder over GF(2m) can be designed with m garbage bits and that of a PB multiplier with 2m garbage bits. To tackle the problem of errors in computation, we also extend the circuit with error detection feature. Gate count and technology oriented cost metrics are used for evaluation. The expression for the upper bound for gate size is also derived for special primitive polynomials. Our technique, when compared with existing CAD tool gives the same gate size and quantum cost.

A Differential Quantizer-Based Error Feedback Modulator for Analog-to-Digital Converters

A differential quantizer-based error feedback modulator intended for digitizing analog signals and its comparison to the traditional interpolative sigma delta analog-to-digital conversion is presented in this brief. The differential quantizer-based error feedback modulator also falls under the class of noise-shaping data converters. This newly introduced technique replaces the integrator with a differential quantizer to achieve noise-shaping characteristics. Thus, integrator associated non-idealities, loop-stability issues, and optimization of the integrator scaling coefficients is no more a concern. Differential quantizer-based error feedback modulator technique can perform well in high-precision and low-power applications. Behavioral-level simulation results demonstrate the mathematical equivalence of the differential quantizer based error feedback modulator technique with interpolative sigma delta modulator technique and confirms its novelty, theoretical stability, and scalability to higher order. The circuit level feasibility and effectiveness of the proposed architecture is verified in a 45-nm CMOS process using a 1-V supply with a power consumption of 0.22 and 0.5 mW for the first and second order modulators, respectively.

A triple-mode feed-forward sigma-delta modulator design for GSM / WCDMA / WLAN applications

This paper presents a cascaded 2-2-2 reconfigurable sigma-delta modulator that can handle GSM, WCDMA and WLAN standards. The modulator makes use of a low-distortion swing suppression topology which is highly suitable for wide band applications. In GSM mode, only the first stage (2nd order ∑-Δ ADC) is turned on to achieve 88dB dynamic range with over-sampling ratio of 160 for a bandwidth of 200KHz; in WCDMA mode a 2-2 cascaded structure (4th order) is turned on with 1-bit in the first stage and 2-bit in the second stage to achieve 74 dB dynamic range with over-sampling ratio of 16 for a bandwidth of 2MHz and a 2-2-2 cascaded MASH architecture with a 4-bit in the last stage to achieve a dynamic range of 58dB for a bandwidth of 20MHz. The novelty lies in the fact that unused blocks of second and third stages can be switched off taking into considerations like power consumption. The modulator is designed in TSMC 0.18um CMOS technology and operates at 1.8 supply voltage.

Wideband low-distortion sigma-delta ADC for WLAN

This work presents a wideband low-distortion sigma- delta analog-to-digital converter (ADC) for wireless local area network (WLAN) standard. The proposed converter makes use of low-distortion swing suppression SDM architecture which is highly suitable for low oversampling ratios to attain high linearity over a wide bandwidth. The modulator employs a 2-2 cascaded sigma-delta modulator with feedforward path with a single-bit quantizer in the first stage and 4-bit in the second stage. The modulator is designed in TSMC 0.18 um CMOS technology and operates at 1.8 V supply voltage. Simulation results show that, a peak SNDR of 57 dB and a spurious free dynamic range (SFDR) of 66 dB is obtained for a 10 MHz signal bandwidth, and an oversampling ratio of 8.