K. Somasundaram

An optimised 3D topology for on-chip communications

Increasing system complexity, energy and device reliability, requirement of modular approach, structured layout, effective spatial reuse of resources, scalability and re-programmability have made network-on-chip (NoC) an obvious interconnection design alternative to the ubiquitous bus based on chip communication architecture in system-on-chip. Designing of a topology and its routing scheme plays a vital role in determining performance of any NoC architecture. In recent years, 3D stacked NoC architecture attracts added interest in NoC design as it offers improved performance and shorter global interconnect. In this paper, we have developed a partially, vertically interconnected 3D topology, namely 3D Recursive Network Topology (3D RNT) and prove that the topology has a Hamiltonian connectedness. We have developed deadlock-free routing algorithm for the 3D RNT topology. Also, we compare the performance of the 3D RNT with partially and fully connected 3D mesh topologies (3D PMT and 3D FMT) by conducting suitable experiments. The experiment results show that there is not much deviation in respect of the performance of the 3D RNT on comparing with 3D PMT and 3D FMT even though a number of vertical links are trimmed down to 75%, which is an encouraging outcome as far as design space is concerned.

Deadlock free routing algorithm for minimizing congestion in a Hamiltonian connected recursive 3D-NoCs

Network on Chip (NoC) has been proposed as a solution for addressing the challenges in System on Chip (SoC) design. Designing a topology and its routing schemes are vital problems in a NoC. One of the major challenges that designers face today in 3D integration is how to route the data packets within a layer and across the layers in a scalable and efficient manner. In any 3D topology, minimizing the amount of data packet transmissions during the routing is still an open problem. Any efficient traditional routing schemes should avoid deadlocks and minimize network congestion from a source node to a destination node. In this paper, we propose a 3D recursive hyper graph Hamiltonian connected network and we propose a deadlock free routing algorithm to minimize congestion in the network. We show that the proposed topology outperforms the topology presented by Dubois et al. (Elevator-First: a Dealock-free distributed routing algorithm for vertically partially connected 3d-Nocs, IEEE Trans. Comput. 62(3) (2013) 609-615) [1] with respect to average network latency. Also, we analysis the delay bound of the switches for the proposed topology and 3D Partially connected Mesh Topology (PMT) and conclude that our topology performs better than 3D PMT.

Deadlock Free Routing Algorithm for Minimizing Data Packet Transmission in Network on Chip

Network on chip NoC has been proposed as a solution for addressing the design challenges of future high performance nanoscale architectures. In NoCs, the traditional routing schemes are routing packets through a single path or multiple paths from one source node to a destination node, minimizing the congestion in the routing architecture. Although these routing algorithms are moderately efficient, they are time dependent. To reduce overall data packet transmission time in the network, the authors consider a network with multiple sources and multiple destinations. Multi-dimensional routing problems appear naturally in several resource allocation problems, communication networks and wireless sensor networks. In this paper, the authors have constructed a deadlock-free multi-dimensional path routing algorithm for minimizing the congestion in NoC.

Performance analysis of cluster based 3D routing algorithms for NoC

In the nano scaled transistors integration era, interconnection of IP blocks and data exchange among the IP blocks are crucial concerns in System on Chip (SoC). Network-on-Chip (NoC) is an on-chip communication methodology proposed to resolve the increased interconnection problems in SoC. In deep sub-micron regime, 3D NoC becomes an emerging research area in recent years as the three dimensional (3D) integrated circuits (ICs) can offer shorter interconnection wire and dissipate lesser power. Major area of the 3D NoC research is network topology and routing techniques. In this paper, we present an NS-2 (Network Simulator) simulation environment for two 3D network topologies (GBT and CBT) and cluster based routing algorithms. Simulation results are reported. Simulation results about the relationship between switch buffer size, injected traffic load, packet delay, packet drop probability and energy dissipation are analyzed. On comparing CBT with GBT, a significant performance improvement is demonstrated.

Design and Evaluation of 3D NoC Routers with Quality-of-Service (QoS) Mechanism for Multi-core Systems

The importance of on-chip communication interconnects was greatly highlighted with the advent of semiconductor technology at nanoscale domain. As the sizes of semiconductor features are reduced day by day, there occurred problems related to wiring. Network-on-Chip architectures are therefore implemented to overcome the wiring issues and have lately been considered as an important area for research. The communication on NoC is carried out in specific topologies by means of routers. In this paper, Partial Mesh of Grid topology (PMG) is considered. We use the Quality of Service (QoS) mechanism to minimize the area and power. PMG-based NoC will give minimum area and power and it reduces the high chances of redundant connections. Throughput and latency are analysed along with other parameters like packet loss ratio and jitter using network simulator NS-2. Area and power analyses are done using Synopsys Design Compiler and PrimeTime PX tool. Our experimental results show that the architecture with QoS mechanism gives a significant reduction in area and power when compared to Region-based Routing (RBR) mechanism. Moreover, the partial mesh of grid topology gives minimal latency and high throughput when compared to mesh of grid topology.

Design and evaluation of virtual channel router for mesh-of-grid based NoC

Network on Chips (NoCs) has now replaced the bus based architectures for communication between different cores in a multiprocessor System on Chip (SoC). NoC integrates SoCs in a better manner. It has the advantage of good scalability and high bandwidth. The communication on NoC is carried out by means of routers. Routers are the back bone of NoC. The design of routers is different for different topologies. In this paper, a Mesh-of-Grid topology is considered. A virtual channel router for mesh of grid topology of NoC is presented here. Area and Power is synthesized for the virtual channel router using Synopsys Design Vision. The experimental results show that the area and power will increase if the bit size of flit is increased.

Total Colorings of Product Graphs

A total coloring of a graph is an assignment of colors to all the elements of the graph in such a way that no two adjacent or incident elements receive the same color. In this paper, we prove Behzad–Vizing conjecture for product graphs. In particular, we obtain the tight bound for certain classes of graphs.

Total Coloring Conjecture for Certain Classes of Graphs

A total coloring of a graph G is an assignment of colors to the elements of the graph G such that no two adjacent or incident elements receive the same color. The total chromatic number of a graph G, denoted by χ ″ ( G ) , is the minimum number of colors that suffice in a total coloring. Behzad and Vizing conjectured that for any graph G, Δ ( G ) + 1 ≤ χ ″ ( G ) ≤ Δ ( G ) + 2 , where Δ ( G ) is the maximum degree of G. In this paper, we prove the total coloring conjecture for certain classes of graphs of deleted lexicographic product, line graph and double graph.

Some Conjectures on Permanents of Doubly Stochastic Matrices

Abstract Let denote the set of all doubly stochastic matrices of order n. Foregger [3] raised a n question whether per per (A) holds for all and , where Jn is the n × n matrix with each entry equal to . But this inequality does not hold good for all matrices in general. In this paper, we consider the above inequality for subpermanents and we provide a sufficient condition for a matrix A ∈ Ωn to satisfy the inequality σk(fJn + (1−t)A) ≤ σk(A) for 0 ≤ t ≤ 1 and discuss the consequences of this inequality.

Total Chromatic Number and Some Topological Indices

Abstract The total chromatic number χ ″ ( G ) of G is the smallest number of colors needed to color all elements of G in such a way that no adjacent or incident elements get the same color. The harmonic index H ( G ) of a graph G is defined as the sum of the weights 2 d ( u ) + d ( v ) of all edges uv of G, where d ( u ) denotes the degree of the vertex u in G. In this paper, we show a relation between the total chromatic number and the harmonic index. Also, we give relations between total chromatic number and some topological indices of a graph.