K. Sonoda

Direct measurement and improvement of local soft error susceptibility in dynamic random access memories

Abstract Soft errors induced in a dynamic random access memory (DRAM) have been measured using a nuclear microprobe. Soft error susceptibility of the local position and structure to the soft error has been clarified. Collection efficiency of charge carriers, induced by incident ions on reverse biased p-n junctions with barrier well structures, has been verified for various implantation doses for well formation.

Well Structure by High-Energy Boron Implantation for Soft-Error Reduction in Dynamic Randam Access Memories (DRAMs)

The susceptibility against soft-errors in dynamic random access memories (DRAMs) has been evaluated using nuclear microprobes by monitoring various addresses of a memory cell array to determine the influence of upper wiring layers such as word lines, bit lines and other patterns. The correlations between irradiated positions of microprobes and monitored cell positions were discussed. The effect of buried implanted layers against carrier collection has also been investigated using ion-beam-induced-current (IBIC) measurement. IBIC measurement revealed that the retrograde well structure was more effective in suppressing soft errors than conventional well structures in bulk or epitaxial substrates.

Estimation of the Charge Collection for the Soft-Error Immunity by the 3D-Device Simulation and the Quantitative Investigation

The charge collection induced by incident particles was estimated by the 3-dimensional device simulation and the quantitative evaluation method using the nuclear microprobe. The role of the buried p +layer was well analyzed in terms of the soft-error immunity of DRAMs. The methods developed here are applicable to optimize the well structure for the soft-error immunity of advanced DRAMs.

Charge Collection Control Using Retrograde Well Tested by Proton Microprobe Irradiation

Soft error reduction by high-energy ion-implanted layers has been investigated by novel evaluation techniques using high-energy proton microprobes. A retrograde well formed by 160 and 700 keV boron ion implantation could completely suppress soft errors induced by the proton microprobes at 400 keV. The proton-induced current revealed the charge collection efficiency for the retrograde well structure. The collected charge for the retrograde well in the soft-error mapping was proved to be lower than the critical charge of the measured DRAMs (dynamic random-access memories). Complementary use of soft-etror mapping and ion-induced-current measurement could clarify well structures immune against soft errors.

Charge collection and soft error in DRAMs investigated using 400 keV proton microprobe

Abstract The charge collection efficiency of diodes with various well profiles has been measured for optimization of the carrier profile for buried layers, formed by high-energy ion-implantation, against soft errors. The charge collection efficiency was calculated using the current induced by incident protons when proton microprobes at 220–400 keV were precisely positioned on the junction of an n+ p diode. The proton-induced current is reduced by a retrograde well structure. The charge collection efficiency is 20–35% lower than that of a conventional well. However, carriers created by incident protons would be easily collected by a buried layer deeper than the created carriers. The results are also supported by charge collection simulation.

Estimation of Carrier Suppression by High-Energy Boron-Implanted Layer for Soft Error Reduction.

Effect of charge-carrier suppression by a high-energy boron-implanted layer has been investigated by ion-induced-current measurement using high-energy proton microprobes. Proton microprobes at 1.3 and 2.0 MeV have been irradiated normal to the n+p diode to generate electron-hole pairs. The collection of charge carriers induced by microprobe irradiation could be reduced by a buried layer formed by boron implantation. It was found that the rate of charge collection depended on the implantation dose but not on the depth of the buried layer.

Ion-induced current measurement for optimization of buried implanted layers against soft errors

Abstract Collection of charge carriers, generated by 2 MeV protons, in n + p diodes with buried conductive layers, formed by high-energy B + implantation, has been investigated using nuclear microprobe (i.e., focused ion beam) induced current-measurement. Suppression efficiency of generated charge carriers was found to depend on the implantation dose for buried wells. About 20% of carriers generated by an incident ion beam could be suppressed by formation of a buried layer, while the suppression rate by the buried layers was increased to about 60% by lowering the applied reverse bias down to 1 V.

Optimization of Buried Implanted Layer in Dynamic Random Access Memories by Soft Error Mapping and Ion Beam-Induced Current

Abstract Soft error testing using scanning nuclear microprobes, i.e., soft error mapping combined with ion beam-induced current (IBIC) measurements, can reveal device immune against soft errors, and, hence, optimal design and process parameters can be determined from the data obtained using nuclear microprobes. Well structures or buried barrier layers to suppress charge carriers, generated by incident energetic particles in DRAMs, have been fabricated by high-energy ion implantation and the suppression efficiency by the well structure was clarified using probe ion-induced current measurement.

Soft-error study of DRAMs using nuclear microprobe

A method for evaluation of soft errors in DRAMs using a nuclear microprobe developed in order to investigate the local sensitive structure is discussed. The susceptibility in the mapping image of a soft error caused by an ion incident onto or near a storage cell in a DRAM can be directly monitored by this method. Soft errors are induced within 4 mu m of the monitored memory cell. The retrograde well formed by MeV ion implantation has experimentally shown a reduction in soft errors. The charge collection into n/sup +/ layers with a retrograde well and a conventional well was estimated through the device simulation. These simulations agreed with the experimental results.<<ETX>>

Optimization of Buried Well Structures in Dynamic Random Access Memories against Soft Error Using Ion Beam Induced Current

The effect of various buried well layers in n + p diodes to suppress the collection of charge carriers, generated by incident ion beams, has been evaluated by ion beam induced current (IBIC) measurements using nuclear microprobes. The behavior of charge carriers, flowing into n + layers of diodes with buried well structures, has also been estimated using a simulator MIDSIP. The suppression efficiency of charge carriers at the n + layer was found to have strong dependence on implanted doses of well structures and applied reverse biases on devices, while that of the diodes with a conventional well was not affected by the reverse bias voltage.