T. Nishimura

Contact resistivity and current flow path at metal/graphene contact

The contact properties between metal and graphene were examined. The electrical measurement on a multiprobe device with different contact areas revealed that the current flow preferentially entered graphene at the edge of the contact metal. The analysis using the cross-bridge Kelvin (CBK) structure suggested that a transition from the edge conduction to area conduction occurred for a contact length shorter than the transfer length of ∼1 μm. The contact resistivity for Ni was measured as ∼5×10−6 Ω cm2 using the CBK. A simple calculation suggests that a contact resistivity less than 10−9 Ω cm2 is required for miniaturized graphene field effect transistors.

Electrical transport properties of graphene on SiO2 with specific surface structures

The mobility of graphene transferred on a SiO2/Si substrate is limited to ∼10 000 cm2V−1s−1. Without understanding the graphene/SiO2 interaction, it is difficult to improve the electrical transport properties. Although surface structures on SiO2 such as silanol and siloxane groups are recognized, the relation between the surface treatment of SiO2 and graphene characteristics has not yet been elucidated. This paper discusses the electrical transport properties of graphene on specific surface structures of SiO2 prepared by O2-plasma treatments and reoxidization.

Metal/graphene contact as a performance Killer of ultra-high mobility graphene analysis of intrinsic mobility and contact resistance

Graphene with a high carrier mobility of more than 10,000 cm2/Vs on SiO2 has attracted much attention as a promising candidate of future high-speed transistor materials. The contact resistance (RC) between graphene and metal electrodes is crucially important for achieving potentially high performance of graphene from both physics and practical viewpoints. This paper discusses metal/graphene contact properties by separating from the intrinsic conduction of graphene.

Ge MOSFETs performance: Impact of Ge interface passivation

We have systematically investigated Ge interface passivation methods, and the highest electron (1920 cm2/Vs) and hole mobility (725 cm2/Vs) have been demonstrated by dramatic reduction of Dit through the collaboration of self-passivation and valency passivation. In Si passivation, it is found that Si contributes to the upper half (worse) and lower one (better) in the bandgap differently. This study strongly suggests us that high performance Ge CMOS is really feasible.

Estimation of residual carrier density near the Dirac point in graphene through quantum capacitance measurement

We discuss the residual carrier density (n*) near the Dirac point (DP) in graphene estimated by quantum capacitance (CQ) and conductivity (σ) measurements. The CQ at the DP has a finite value and is independent of the temperature. A similar behavior is also observed for the conductivity at the DP, because their origin is residual carriers induced externally by charged impurities. The n* extracted from CQ, however, is often smaller than that from σ, suggesting that the mobility in the puddle region is lower than that in the linear region. The CQ measurement should be employed for estimating n* quantitatively.

Comprehensive study of GeO 2 oxidation, GeO desorption and GeO 2 -metal interaction -understanding of Ge processing kinetics for perfect interface control-

Based on the understanding of kinetic views of GeO desorption from GeO<inf>2</inf>/Ge stacks, thermodynamic control of the qualities of both GeO<inf>2</inf> films and GeO<inf>2</inf>/Ge interfaces was demonstrated. It was proposed to characterize the effects of GeO desorption on GeO<inf>2</inf> by the optical absorption. In addition, MIS band alignment was also discussed from the viewpoint of the effects of metal-GeO<inf>2</inf> interaction at the top interface.

Intrinsic graphene/metal contact

This paper presents our recent understanding of metal/graphene contact in terms of intrinsic interface obtained from the comparison between resist-free and conventional EB processes, and discusses future challenges to reduce the contact resistivity.

Carrier density modulation in graphene underneath Ni electrode

We investigate the transport properties of graphene underneath metal to reveal whether the carrier density in graphene underneath source/drain electrodes in graphene field-effect transistors is fixed. The resistance of the graphene/Ni double-layered structure has shown a graphene-like back-gate bias dependence. In other words, the electrical properties of graphene are not significantly affected by its contact with Ni. This unexpected result may be ascribed to resist residuals at the metal/graphene interface, which may reduce the interaction between graphene and metals. In a back-gate device fabricated using the conventional lithography technique with an organic resist, the carrier density modulation in the graphene underneath the metal electrodes should be considered when discussing the metal/graphene contact.

Electron mobility in high-k Ge-MISFETs goes up to higher

This paper will first discuss intrinsic advantages of high-pressure oxidation of Ge and then present further improvement of electron mobility in Ge n-MISFET using high-k gate stacks combined with high-pressure oxidation. The peak mobility is about 1500 cm2/Vsec, which is the highest one to date among unstrained Si and Ge MISFETs. Ge-CMOS is a strong candidate for beyond Si-CMOS.

Design and demonstration of reliability-aware Ge gate stacks with 0.5 nm EOT

This paper reports a novel material/process-based design for reliability-aware Ge gate stack for the first time. Initially good characteristics of Ge gate stacks do not necessarily guarantee the long-term device reliability. To overcome the big hurdle, we have investigated the stability of GeO2 network as well as the formation of new high-k. The very robust Ge gate stack with both 0.5 nm EOT and sufficiently low Dit is demonstrated.