Arun Virupaksha Gowda

Low inductance power module with blade connector

A novel single-switch power module has been developed, featuring a laminated blade connector for low inductance interconnect to a busbar. The module was designed, optimized and experimentally validated as part of a high frequency three-phase converter, demonstrating parasitic inductances of less than one nano henry for the module and as low as five nano henries for the converter phase-leg commutation loop. The flexible plug-in hardware facilitated direct comparison of switching performance between three different chipsets, including a 150A and a 300A hybrid designs using the fastest 1200V silicon IGBTs with silicon carbide (SiC) Schottky diodes, as well as a 150A all-SiC module with emerging SiC MOSFETs. The results were also compared with switching performance of standard modules. First, the impact of parasitic inductance on switching performance was quantified by testing the same 300A hybrid chipset in an industry-standard module. Compared to the low inductance blade POL module, the standard module had 65% higher voltage overshoot and 30% higher total switching losses. Second, the switching performance of the 150A, 1200V fast IGBT, in either standard silicon or the hybrid blade module, was compared with the all-SiC blade module under the same test conditions. The IGBT switching losses of the standard silicon module were 3.5 times higher, while the hybrid blade module losses were 2.5 times higher than those of the all-SiC module. The new low inductance blade module is an excellent package for the new generation of fast silicon IGBTs and the emerging SiC power devices. The module will enable efficient power conversion at significantly higher switching frequencies and power densities.

Voids in thermal interface material layers and their effect on thermal performance

One of the key challenges in the thermal management of microelectronic devices is interfaces such as those between the chip and heat spreader and between the heat spreader and heat sink or cold plate. Typically, thermal interfaces are filled with materials such as thermal adhesives and greases. Interface materials reduce the contact resistance between the mating heat generating and heat sinking units by filling voids and grooves created by the nonsmooth surface topography of the mating surfaces, thus improving surface contact and the conduction of heat across the interface. With shrinking thermal budgets, the role of these layers in the cooling of microelectronic devices has become more critical. Voids in thermal interface material (TIM) layers may be trapped during the flow of the TIM during assembly, due to outgassing during the curing process, or due to insufficient volume. The negative effect of such voids on the thermal resistance of a TIM layer can be devastating. In applications where the TIM performs the function of a structural adhesive, voids may negatively affect the adhesion strength and reliability of the TIM layer. In this work, the effect of voids and their characteristics on the thermal performance of thermal interface adhesive layers is reported.

Performance and Reliability of SiC MOSFETs for High-Current Power Modules

We address the two critical challenges that currently limit the applicability of SiC MOSFETs in commercial power conversion systems: high-temperature gate oxide reliability and high total current rating. We demonstrate SiC MOSFETs with predicted gate oxide reliability of >106 hours (100 years) operating at a gate oxide electric field of 4 MV/cm at 250°C. To scale to high total currents, we develop the Power Overlay planar packaging technique to demonstrate SiC MOSFET power modules with total on-resistance as low as 7.5 m. We scale single die SiC MOSFETs to high currents, demonstrating a large area SiC MOSFET (4.5mm x 4.5 mm) with a total on-resistance of 30 m, specific on-resistance of 5 m-cm2 and blocking voltage of 1400V.

Integral micro-channel liquid cooling for power electronics

A novel integral micro-channel heat sink was developed, featuring an array of sub-millimeter channels fabricated directly in the back-metallization layer of the direct bond copper or active metal braze ceramic substrate, thus minimizing the material between the semiconductor junction and fluid and the overall junction-to-fluid thermal resistance. The ceramic substrate is bonded to a baseplate that includes a set of interleaved inlet and outlet manifolds for uniform fluid distribution across the actively cooled area of the heat sink. The interleaved manifolds greatly reduce the pressure drop and minimize temperature gradient across the heat sink surface. After performing detailed simulations and design optimization, a 200 A, 1200 V IGBT power module with the integral heat sink was fabricated and tested. The junction-to-fluid thermal resistivities for the IGBTs and diodes were 0.17°C⋆cm2/W and 0.14°C⋆cm2/W, respectively. The design is superior to all reported liquid cooled heat sinks with a comparable material system, including the micro-channel designs. It is also easily scaleable to larger heat sink surfaces without compromising the performance.

Micron and Submicron-Scale Characterization of Interfaces in Thermal Interface Material Systems

One of the key challenges in the thermal management of electronic packages are interfaces, such as those between the chip and heat spreader and the interface between a heat spreader and heat sink or cold plate. Typically, thermal interfaces are filled with mate-rials such as thermal adhesives and greases. Interface materials reduce the contact resistance between the mating heat generating and heat sinking units by filling voids and grooves created by the nonsmooth surface topography of the mating surfaces, thus improving surface contact and the conduction of heat across the interface. However, micron and submicron voids and delaminations still exist at the interface between the interface material and the surfaces of the heat spreader and semiconductor device. In addition, a thermal interface material (TIM) may form a filler-depleted and resin-rich region at the interfaces. These defects, though at a small length scale, can significantly deteriorate the heat dissipation ability of a system consisting of a TIM between a heat generating surface and a heat dissipating surface. The characterization of a freestanding sample of TIM does not provide a complete understanding of its heat transfer, mechanical, and interfacial behavior. However, system-level characterization of a TIM system, which includes its freestanding behavior and its interfacial behavior, provides a more accurate understanding. While, measurement of system-level thermal resistance provides an accurate representation of the system performance of a TIM, it does not provide information regarding the physical behavior of the TIM at the interfaces. This knowledge is valuable in engineering interface materials and in developing assembly process parameters for enhanced system-level thermal performance. Characterization of an interface material between a silicon device and a metal heat spreader can be accomplished via several techniques. In this research, high-magnification radiography with computed tomography, acoustic microscopy, and scanning electron microscopy were used to characterize various TIM systems. The results of these characterization studies are presented in this paper. System-level thermal performance results are compared to physical characterization results.

Realizing the full potential of silicon carbide power devices

Silicon carbide (SiC) MOSFET power devices are expected to replace silicon IGBTs in power electronics applications requiring higher efficiency and power density, as well as capability to operate at higher temperatures. This paper reports on the development of high efficiency SiC power MOSFETs, power modules and switching converters at GE. The prototype 30A, 1200V discrete devices have on-resistance below 50 mΩ and the total switching energy of 0.6 mJ, offering performance superior to any competing 1200V devices. A back-to-back buck-boost converter was built using 15A MOSFETs and experimental results are presented. The 15A devices were also used for fabrication of 150A all-SiC modules. The modules have 10 mΩ on-resistance and the total switching energy is 3.3 mJ, both significantly better than competing designs. The results demonstrate the full potential of the SiC devices for power conversion applications.

Utilization of carbon fibers in thermal management of microelectronics

Power dissipation is expected to increase exponentially to 150-250 W per chip over the next decade. To manage this large heat output, it is necessary to minimize the thermal resistance between the chip and a heat dissipation unit that the device is attached to. It is therefore important to further improve the thermal performance of thermal interface materials (TIMs), which can be achieved through 1) improvement of the bulk thermal conductivity of TIMs; and/or 2) reduction of interfacial thermal resistances between the TIM and the device and/or TIM and the heat dissipation unit. The latter improvement may be obtained by enhanced physical properties of TIMs (e.g., viscosity or wetting ability) and/or surface modification of the heat dissipation unit or the inactive side of the device. Researchers have tried to take advantage of the high 1D thermal conductivities of graphite fibers, and more recently of carbon nanotubes (CNT), to reduce the thermal resistance between the chip and the heat dissipation unit. The efforts can be classified into three categories: 1) Forming pre-aligned graphite fiber or CNT films that have high bulk thermal conductivities in the heat transport direction, and applying such films as TIMs; 2) incorporating randomly oriented graphite fibers or CNT into silicone or epoxy matrices in the presence or absence of a second filler to improve bulk thermal conductivities, and applying the thus-formed blend as thermal greases, or adhesives or gels; and 3) growing CNT or graphite fibers from the heat sink/spreader surface and/or silicon backside and assembling them together with a TIM a to increase the bulk heat transport property and reduce the interfacial resistances, In this paper, we will present results for each of the three approaches, and discuss the challenges facing each one.

Reliability of POL-kw power modules

Wide band gap (WBG) semiconductor devices have demonstrated superior electrical and thermal performance, compared to their silicon-based counterparts. However, innovative power module packaging design and materials suitable to WBG devices are required. In this paper, the development of a new high power density module using the Power Overlay (POL) packaging platform is presented. The wirebond-less packaging platform has shown significantly reduced electrical parasitics, while providing a thin profile to allow double-side cooling and the integration of gate drive circuits. Thermal cycling and high temperature storage tests were conducted on specimens fabricated and assembled by production equipment. The results presented here were used to establish design guidelines for reliable operation of POL-based power modules.

Spherical boron nitride fillers for high performance thermal greases

Highly efficient thermal interface materials (TIMs) have become necessary to effectively manage the increasing heat generated at the silicon level with every new generation of microprocessors. Typically, TIMs consist of polymers that are highly loaded with thermally conductive fillers. Boron nitride (BN) fillers have been employed as a thermal conductive filler for TIMs for decades. However, conventional boron nitride fillers were largely anisotropic in nature. A novel spherical BN filler is presented as an isotropic thermally conductive filler for TIMs and the thermal and reliability performance characteristics of spherical BN filled high thermal performance greases are described

Component embedding platform for thin profile SiP, POP and fan-out WLP

While component embedding technologies have reached maturity and are used for high volume manufacturing, the industry is looking for new ways to exploit the possibilities it enables. Growing interest in embedding is introducing new challenges, requiring further innovation and pushing development of solutions that offer cost efficient and robust manufacturing processes for novel product designs. High quality and high yield production processes are essential for all embedding technologies, but it is equally important to have a flexible supply solution, which lowers the barrier for adoption and enables short cycle time from early product concept to prototyping and manufacturing. The Power Overlay (POL) technology has been developed to improve product performance and miniaturization using a direct microvia and polyimide (PI) based interconnection technology. The POL is a platform of packaging technology solutions for wide application area. Different POL adaptations and target applications will be briefly reviewed in this paper. A new Ultra-Thin WLPOL process has been developed and will be presented in the paper. The technology feasibility for sub 200μm fan-out WLP package has been demonstrated using 6×6mm, 90×9mm, 10×10mm, and 12×12mm package configurations.