K. Van Schuylenbergh

Comparison of PbI2 and HgI2 for direct detection active matrix x-ray image sensors

The factors determining the x-ray sensitivity of HgI2 and PbI2 as direct detector materials for large area matrix addressed x-ray image sensors are described, along with a model to explain their different properties. The imaging studies are made on test arrays with 512×512 pixels of size 100 μm. The x-ray sensitivity and spatial resolution are reported, along with measurements of the various mechanisms that influence the sensitivity, such as charge collection, x-ray absorption, fill factor, and image lag. The spatial resolution of PbI2 decreases with increasing film thickness, but this effect is not observed in HgI2. The x-ray response data are used to compare the sensitivity to the theoretical values for the ionization energy and to identify the various loss mechanisms. We find that the sensitivity of HgI2 can be explained by a few small and well characterized loss factors. This material exhibits good spatial resolution, high fill factor, and high charge collection. PbI2 films exhibit lower sensitivity, ...

Out-of-plane high-Q inductors on low-resistance silicon

Integrated high-Q coils are much sought after because they enable high-quality radio-frequency circuits that do not rely on off-chip discretes. We present a novel surface micro-machined inductor with its coil axis parallel to the substrate plane. Coils fabricated on standard unaltered low-resistance silicon exhibit record-high-quality factors (Q) of over 70 at 1 GHz. The devices are made by three-dimensional (3-D) self-assembly of stress-engineered structures fabricated with standard semiconductor batch processing techniques. We also designed, fabricated, and characterized silicon Bi-CMOS L-C oscillators built around these coils. Compared side by side against state-of-the-art planar spirals, they produce a 12.3 dB lower phase noise at 100 kHz offset, and 14.6 dB after normalizing to frequency and power.

Flat panel imagers with pixel level amplifiers based on polycrystalline silicon thin-film transistor technology

We report here the realization of a large-area compatible, flat panel imager with pixel level amplifiers. The imager is based on excimer-laser crystallized, polycrystalline silicon (poly-Si) thin-film transistors. By incorporating pixel level amplification, flat panel imagers are expected to be able to achieve unprecedented noise performance, with the hope of achieving single photon detection. We have demonstrated good noise performance of 1300 erms, exceeding the commonly accepted industry standard of 2000 erms. We also briefly discuss the source of the extra noise, as well as the possibility of further reducing the noise level.

High Resolution, High Fill Factor A-SI:H Sensor Arrays for Optical Imaging

Amorphous silicon large area sensor arrays are in production for x-ray medical imaging. The most common pixel design works very well for many applications but is limited in spatial resolution because the available sensor area (the fill factor) vanishes in small pixels. One solution is a 3-dimensional structure in which the sensor is placed above the active matrix addressing. However, such high fill factor designs have previously introduce cross talk between pixels. We present data for a design in which the a-Si:H p-i-n photodiode sensor layer has a continuous i-layer and top p + -layer, and a patterned n + -layer contact to the pixel. Arrays of 64 μm and 75μm pitch have been fabricated and are the highest resolution a-Si:H arrays reported to date. The resolution matches the pixel size, and sensitivity has been improved by the high fill factor. Comparison is made between arrays with standard TFTs and TFTs with self-aligned source and drain contacts. Data line capacitance is improved by use of the self-aligned contacts. Measurements are included on the contact to bias capacitance. The high fill factor design greatly suppresses lateral leakage currents, while retaining ease of processing. Provided illumination levels remain below saturation, the resolution matches expectation for the pixel size.

Wafer-Level Packaging With Soldered Stress-Engineered Micro-Springs

Micro-springs for integrated circuit test and packaging are demonstrated as soldered flip chip interconnects in a direct die to printed circuit board package. The spring interconnects are fabricated with thin film metallization as the last step in a wafer-scale process. The z-compliance of the interconnects can be used to test and/or burn-in parts in wafer form. After the parts are diced from the wafer, the springs then become the first-level (and often the last-level) interconnect between the chip and the board. The xy-compliance of the interconnect enables considerably large die to be soldered to an organic printed circuit board without underfill using a surface mount compatible process. To demonstrate this concept, daisy chain test vehicles were fabricated on die measuring 11.5 mm times 6.5 mm with 48 spring contacts on a 0.8 mm times 0.65 mm grid array, each spring measuring 400 mum times 100 mum. The parts were placed onto organic boards with screen printed solder paste using a pick and place machine. The parts were reflowed to complete the solder connection to each spring using eutectic and lead-free solder. Assembled parts have undergone >20 000 hot plate thermal cycles and >1000 oven thermal cycles without failure.

Solder-Free Pressure Contact Micro-Springs in High-Density Flip-Chip Packages

This work investigates electrical pressure contacts based on a micro-spring with orders of magnitude smaller pitch and force than conventional pressure contacts. Flip-chip packages were assembled with hundreds of micro-springs at 20 mum pad-pitch, 40 mum spring-pitch, and an operating force of 0.01 gram on gold pads. These packages are shown to have stable resistance values during both in-situ thermocycle (0 degC to 125 degC) and humidity testing (60 degC at 95% RH). High-speed glitch measurements are performed to confirm the pressure contact does not have intermittent opens during thermocycling. These results suggest that a low-force solder-free pressure spring contact is a viable technology for next generation flip-chip packaging

On-chip out-of-plane high-Q inductors

Integrating high-Q inductors on semiconductor circuits has been an elusive goal for years due primarily to the eddy current losses and skin effect resistance associated with in-plane spiral inductors. Three-dimensional out-of-plane coils reduce eddy current and skin effect losses by virtue of their geometry and magnetic field orientation. However, out-of-plane coils were not deemed producible by standard semiconductor fabrication methods. This paper reports on a novel use of conventional semiconductor processing techniques to batch-fabricate three-dimensional high-Q inductors on a wide range of insulating or active semiconductor substrates. Thin molybdenum-chromium films are sputter deposited with an engineered built-in stress gradient so that, when patterned and released from their substrate, they curl into circular springs. These springs self-assemble into three-dimensional scaffolds that form highly conductive windings after being copper plated. Quality factors up to 85 are observed at 1 GHz on standard CMOS silicon. The in-circuit microcoil performance is also compared in BiCMOS silicon L-C oscillators to that of state-of-the-art planar spirals with slotted grounds.

Laser processing of amorphous silicon for large-area polysilicon imagers

Pulsed excimer-laser processing of amorphous silicon on non-crystalline substrates allows for the fabrication of high-quality polysilicon materials and thin-film transistors (TFTs). Under optimized processing conditions, these polysilicon TFTs have high mobilities, sharp turn-on, low off-state leakage currents and good spatial uniformity. These improved parameters, particularly the low off-state leakage currents and good uniformity, enable, not only displays, but also the more demanding flat-panel imaging arrays to be fabricated in polysilicon, and results on an imager are presented.

Crosstalk and lateral conduction effects in continuous-sensor amorphous silicon imagers

Studies are reported of the image-blur effects caused by lateral crosstalk between neighboring pixels of large-area amorphous silicon (a-Si:H) image sensors. Data are obtained from high fill factor sensor arrays using 512×512 pixels of 75 μm size and a pixel gap of 10 μm. Measurements of the line-spread function determine the charge transfer from the illuminated pixel to neighboring ones along both array orientations, and for different samples and operating conditions. The lateral conduction is attributed to three effects: conduction along the interface between the a-Si:H film and the underlying passivation; field-dependent electron injection at the edge of the sensor; and field enhancement of the interface conduction due to the bias applied to the address lines. We show that the crosstalk can be controlled by the choice of operating conditions and optimization of the materials.

Pulsed laser crystallization of amorphous silicon for polysilicon flat panel imagers

Pulsed excimer-laser processing of amorphous silicon on glass substrates enables the fabrication of high-quality polycrystalline silicon (poly-Si) thin-film transistors. Here we describe the fabrication and testing of prototype imagers fabricated in CMOS poly-Si using a low-temperature, laser-crystallization process on glass substrates. Integrated shift registers and buffers for driving the gate lines of the array and integrated multiplexers on the data lines have been produced and are shown to run the imagers successfully without using external gate-line electronics. In addition, a three-transistor poly-Si circuit has been fabricated at each pixel, providing a charge gain of 11 for the small photo signal and a low noise level of 1200 electrons RMS.