K.W. Current

Current-mode CMOS multiple-valued logic circuits

Current-mode CMOS circuits are receiving increasing attention. Current-mode CMOS multiple-valued logic circuits are interesting and may have applications in digital signal processing and computing. In this paper we review several of the current-mode CMOS multiple-valued logic (MVL) circuits that we have studied over the past decade. These circuits include a simple current threshold comparator, current-mode MVL encoders and decoders, current-mode quaternary threshold logic full adders (QFAs), current-mode MVL latches, current-mode latched QFA circuits, and current-mode analog-to-quaternary converter circuits. Each of these circuits is presented and its performance described. >

An image processing IC for backprojection and spatial histogramming in a pipelined array

The first VLSI digital signal processor that performs both high-precision image backprojection and spatial histogram calculations at raster-scan rates as high as 30 MHz is described. Realized in 1 mu m CMOS technology, this 13.3 mm*13.3 mm chip is designed to handle images as large as 1024*1024 12 b pixels. Loadable coefficients and a unified architecture allow this IC to be used with a variety of computed-tomography scanners for image reconstructions, including fan- and parallel-beam reconstruction. This chip also computes the forward Radon transform, which is a spatial histogram, permitting it to be used for iterative reconstruction algorithms. The bit lengths in the fixed-point architecture assure 12 b reconstruction accuracy. >

High-speed computation of the Radon transform and backprojection using an expandable multiprocessor architecture

The accuracy and speed characteristics of implementations of several line integration models required for Radon (1917) transform (used for computed tomography image reconstruction) and backprojection computations are described and compared. The fixed-point number system used is evaluated by error comparisons to identical floating-point calculations. An expandable multiprocessor architecture for high-speed computation that has been realized as a prototype using commercially available digital signal processor (DSP) chips as the basic processing elements is described. The simulated performances of two popular DSP chips for this application are discussed and compared. Performance characteristics of the complete prototype hardware system are presented. The computational speed of a four-chip system is measured to be more than 190 times better than that of a Sun 3/160 with a math coprocessor. The architecture and prototype organization are not dependent on the DSP chip chosen, and substitution of the most up-to-date DSP chips can yield even better speed performance. >

CMOS current-mode circuits for neural networks

Current-mode CMOS multiple-valued logic circuits that are compatible with many previously proposed CMOS artificial neural network circuits are discussed. Current-mode circuitry for generating multiple-valued weighted sums of currents, performing arithmetic operations, and for comparing multiple-valued (quantized) signal currents to action threshold current are presented. Memory circuits capable of storing the multiple-valued currents are presented. An experimental evaluation of several of the circuits is presented.<<ETX>>

VLSI architecture for high-speed image reconstruction: considerations for a fixed-point architecture

The amount of data generated by computed tomography (CT) scanners is enormous, making the image reconstruction operation slow, especially for 3-D and limited-data scans requiring iterative algorithms. The inverse Radon transform, commonly used for CT image reconstructions from projections, and the forward Radon transform are computationally burdensome for single-processor computer architectures. Fortunately, the forward Radon transform and the back projection operation (involved in the inverse Radon transform) are easily calculated using a parallel pipelined processor array. Using this array the processing time for the Radon transform and the back projection can be reduced dramatically. This paper describes a unified, pipelined architecture for an integrated circuit that computes both the forward Radon transform and the back projection operation at a 10 MHz data rate in a pipelined processor array. The trade-offs between computational complexity and reconstruction error of different interpolation schemes are presented along with an evaluation of the architectures noise characteristics due to finite word lengths. The fully pipelined architecture is designed to reconstruct 1024 pixel by 1024 pixel images using up to 1024 projections over 180 degrees. The chip contains three pipelined data-paths, each five stages long, and uses a single multiplier.

A VLSI architecture for two-dimensional Radon transform computations

A unified Radon-transform/back-projection IC that is capable of performing the forward Radon transform and back-projection computations in a multiprocessor array architecture is being designed in a CMOS technology. The architecture of the IC and related design considerations are presented. This chip would make possible high-quality image reconstruction to 12-b resolution at video rates.<<ETX>>

A unified DCT/IDCT architecture for VLSI implementation

A unified discrete cosine transform/inverse discrete cosine transform (DCT/IDCT) architecture suitable for VLSI implementation is presented. A single VLSI NMOS chip design and layout for realizing this architecture is described. Algorithm simulations and experimental performance of integrated test subcircuits indicate that this chip would be capable of real-time processing of 10-MHz video signals. It is considered that circuits of this type could be very useful in real-time image data compression.<<ETX>>

On behavioral modeling of analog and mixed-signal circuits

Behavioral simulation of complex, inherently highly nonlinear mixed-signal systems is often the only effective way to evaluate possible system performance before fabrication and characterization of the hardware system. Transistor-level, SPICE, simulations of these systems are often practically impossible because of the enormous computational time required due to the many interactions of all the nonlinearities and the widely separated system time constants. New behavioral models for useful electronic functions have been developed as straightforward mathematical descriptions that can be evaluated by general purpose mathematical programs and system simulators. The models are targeted for MATLAB and use standard MATLAB expressions and linked C and FORTRAN codes. An example PLL behavioral model is presented and evaluated by comparing simulated performance to actual experimental integrated circuit performance.<<ETX>>

A CMOS continuous-time NTSC-to-color-difference decoder

A continuous-time NTSC-to-color-difference decoder has been fabricated in a 2-/spl mu/m CMOS process. The 9-mm/sup 2/ decoder includes the chrominance IF filter, automatic gain control, timing recovery, 90/spl deg/ phase shift, demodulators, hue and saturation controls. The 90/spl deg/ phase-shift circuit is based on peak detection and is used for tuning the chrominance IF filter and demodulation of the R-Y signal. The total power dissipation is 45 mW on /spl plusmn/2.5-V supplies. All circuits are fully differential. This allows the timing-recovery outputs to achieve a differential phase of 0.1/spl deg/ over a horizontal-line interval. For a standard NTSC 1 V/sub p-p/ color-bar input, the R-Y and B-Y outputs exhibit maximum phase and gain errors of 1.1/spl deg/ and 1.5/spl deg/, respectively.

A pipelined VLSI chip architecture for real-time computed tomography of fan-beam data

Image reconstruction from projection data is very computationally intensive. A novel IC architecture is presented which can be used in a pipeline of identical ICs to reconstruct images from parallel- and fan-beam scanner configurations. The accuracy and the finite word-length effects of fan-beam reconstruction are considered. Software simulations of the architecture designed in a 1 mu m CMOS technology show that a maximum clock speed of 40 MHz is possible under nominal operating conditions.<<ETX>>