I. Agi

An image processing IC for backprojection and spatial histogramming in a pipelined array

The first VLSI digital signal processor that performs both high-precision image backprojection and spatial histogram calculations at raster-scan rates as high as 30 MHz is described. Realized in 1 mu m CMOS technology, this 13.3 mm*13.3 mm chip is designed to handle images as large as 1024*1024 12 b pixels. Loadable coefficients and a unified architecture allow this IC to be used with a variety of computed-tomography scanners for image reconstructions, including fan- and parallel-beam reconstruction. This chip also computes the forward Radon transform, which is a spatial histogram, permitting it to be used for iterative reconstruction algorithms. The bit lengths in the fixed-point architecture assure 12 b reconstruction accuracy. >

High-speed computation of the Radon transform and backprojection using an expandable multiprocessor architecture

The accuracy and speed characteristics of implementations of several line integration models required for Radon (1917) transform (used for computed tomography image reconstruction) and backprojection computations are described and compared. The fixed-point number system used is evaluated by error comparisons to identical floating-point calculations. An expandable multiprocessor architecture for high-speed computation that has been realized as a prototype using commercially available digital signal processor (DSP) chips as the basic processing elements is described. The simulated performances of two popular DSP chips for this application are discussed and compared. Performance characteristics of the complete prototype hardware system are presented. The computational speed of a four-chip system is measured to be more than 190 times better than that of a Sun 3/160 with a math coprocessor. The architecture and prototype organization are not dependent on the DSP chip chosen, and substitution of the most up-to-date DSP chips can yield even better speed performance. >

VLSI architecture for high-speed image reconstruction: considerations for a fixed-point architecture

The amount of data generated by computed tomography (CT) scanners is enormous, making the image reconstruction operation slow, especially for 3-D and limited-data scans requiring iterative algorithms. The inverse Radon transform, commonly used for CT image reconstructions from projections, and the forward Radon transform are computationally burdensome for single-processor computer architectures. Fortunately, the forward Radon transform and the back projection operation (involved in the inverse Radon transform) are easily calculated using a parallel pipelined processor array. Using this array the processing time for the Radon transform and the back projection can be reduced dramatically. This paper describes a unified, pipelined architecture for an integrated circuit that computes both the forward Radon transform and the back projection operation at a 10 MHz data rate in a pipelined processor array. The trade-offs between computational complexity and reconstruction error of different interpolation schemes are presented along with an evaluation of the architectures noise characteristics due to finite word lengths. The fully pipelined architecture is designed to reconstruct 1024 pixel by 1024 pixel images using up to 1024 projections over 180 degrees. The chip contains three pipelined data-paths, each five stages long, and uses a single multiplier.

A VLSI architecture for two-dimensional Radon transform computations

A unified Radon-transform/back-projection IC that is capable of performing the forward Radon transform and back-projection computations in a multiprocessor array architecture is being designed in a CMOS technology. The architecture of the IC and related design considerations are presented. This chip would make possible high-quality image reconstruction to 12-b resolution at video rates.<<ETX>>

A comparison of analog DFE architectures for disk-drive applications

Analog equalizers offer potentially higher speed, lower power and smaller die area than their digital counterparts. Assuming adequate analog forward equalizers are available, we present different integrated circuit (IC) architectures for analog-based decision feedback equalizers, and the strengths and weaknesses of each implementation are discussed.<<ETX>>

An expandable VLSI processor array approach to contour tracing

A new architecture for contour tracing of black-and-white images is described. This architecture uses parallelism and pipelining to achieve a significant increase in processing speed over previous tracers. An array of identical processors suitable for VLSI implementation is used. The array approach facilitates expansion to handle arbitrarily large images. The processors trace independently, thereby providing fully parallel, high-speed operation. A postprocessor links the partial contours created by the subdivision of the input image. Simulation results for compression ratio and number of operations are presented.<<ETX>>

A VLSI processor for parallel contour tracing

A custom IC processor that traces contours in black-and-white images is described. The CMOS IC contains a finite state machine, an arithmetic logic unit (ALU), an input delay line, and RAM. Each process extracts the edges from a rectangular portion of the input image and traces the edges, producing a description of the contours. A complete tracing system employs an array of these processors. The array architecture allows expansion to handle arbitrarily large images. The processors trace independently, thereby providing fully parallel high-speed operation. Partial contours are generated as a result of the partitioning of the image among the processors. A postprocessor links any partial contours created by the subdivision of the input image. The contour-tracing algorithm and simulation results for compression ratio and number of operations are presented. The architecture and measured performance of the IC are described. >

A pipelined VLSI chip architecture for real-time computed tomography of fan-beam data

Image reconstruction from projection data is very computationally intensive. A novel IC architecture is presented which can be used in a pipeline of identical ICs to reconstruct images from parallel- and fan-beam scanner configurations. The accuracy and the finite word-length effects of fan-beam reconstruction are considered. Software simulations of the architecture designed in a 1 mu m CMOS technology show that a maximum clock speed of 40 MHz is possible under nominal operating conditions.<<ETX>>

A 450 Mops Image Backprojector And Histogrammer

A new VLSI chip performs both image backprojection and spatial histogram calculations at raster-scan rates as high as 30 MIIz. Realized in 1 pm CMOS technology, this 13.3mm x 13.3mm chip is designed to handle images as large as 1024 x 1024 12-bit pixels. Loadable coefficients allow this chip to be used with a variety of computed-tomography scanners for image reconstruction, including fan-beam reconstruction. The bit lengths in the fixed-point architecture assure 12-bit reconstruction accuracy.

A high-speed Radon transform and backprojection processor

An expandable multiprocessor hardware system for the computation of the Radon transform and backprojection equations is described. The system is constructed with commercially available digital signal processing (DSP) chips. This Radon transform processor is based upon a parallel-pipelined multiprocessor architecture. Performance characteristics of the hardware system are presented.<<ETX>>