K. Y. Yow

Laser grooving characterization for dicing defects reduction and its challenges

Blade sawing has been widely used in semiconductor industry and it is the most conventional process in semiconductor manufacturing to produce singulated ICs. This well established dicing technique poses challenges to process next generation of wafer when the wafer fabrication technology is fast scaling down in node size to 90-, 45-, 32-and 22-nm where low-k dielectric is used. ILD (Inter-Layer Dielectric) and metal layers peelings, cracks, chipping, and delamination are the most common dicing defects observed on low-k wafer processed by the traditional blade sawing techniques. This paper presents an experimental study to improve the dicing performance and quality on processing low-k wafer by using a combination of laser grooving process and traditional blade sawing technique. Some low-k wafers were used as test vehicles. The laser process outcomes and responses are governed by the changes of process input parameters such as laser power, repetition rate, grooving feed speed, defocus amount and street index. The effects of the process parameters on the laser kerf geometry, grooving edge quality and defects are evaluated by using optical microscopy and scanning electron microscopy (SEM). Experimental results have shown that the dicing quality produced by using a combination of laser grooving and blade sawing technique can significantly minimize the dicing defects. It is one of the potential solutions to address the quality and yield issues in low-k wafer dicing. The key challenges of laser grooving and recommended future development works are discussed.

Wafer dicing process optimization and characterization for C90 low-k wafer technology

This paper presents an investigation on the effect and optimization of machining parameters for 90nm low-k wafer topside peeling improvement in mechanical dicing operation. It is part of the continuous improvement that performed based on current established dicing recipe. The resulted outcomes to achieve are cut quality improvement, dicing yield loss reduction and device reliability enhancement for low-k wafer dicing. The experimental studies were conducted under varying table speed, Z1 spindle rotation as well as the Z1 cut depth was examined. The settings of machining parameters were determined by using design of experiment (DOE) techniques and the critical process parameters were determined and analyzed statistically by using analysis of variance (ANOVA). Optical visual inspection was conducted on post-processed low-k test wafers and several of scribe structures which comprised of different level of metal density, for a through quantification and categorization on the peeling mode. Worst case peeling measurements and characterizations were conducted by using optical microscope, scanning electron microscopy (SEM) and focused ion beam (FIB). Electrical test and device reliability assessments were conducted to reflect and confirm the improvement of the samples diced with optimized mechanical dicing process. As a result, the optimum dicing parameters to apply in production environment was realized and established in order to overcome the quality obstacles and yield loss issue in low-k wafer dicing.

Investigations of the effects of blade type, dicing tape, blade preparation and process parameters on 55nm node low-k wafer

This paper presents an investigation of the effects of blade type, dicing tape, blade preparation and the key process parameters optimization on improving topside ILD peeling (thicker scribe structures) and chipping for 55nm low-k wafer. An appropriate dicing blade selection, blade preparation / conditioning methodology and dicing tape selection plays an important role in developing a robust saw process. As such, experimental studies were conducted under varying Z1 spindle rotation, Z1 cut depth into Si as well as the blade type property variation as the input factors, in order to improve the ILD peeling and die chipping. The settings of machining parameters and blade types were determined by using the design of experiment (DOE) techniques and the critical process parameters and materials were analyzed statistically by using the analysis of variance (ANOVA). Dicing tape property variations (PO-base or PVC-base) as well as the blade preparation methodology posed some influences on the overall dicing quality, such as die backside chipping, die removal performance, ILD peeling and die topside chipping. SEM imaging and optical visual inspection were conducted to validate the impacts of the ILD peeling / chipping on post-processed low-k wafers. A thorough quantification and categorization of ILD peeling and chipping on heavy metallization at the saw scribe structures were described. As part of the recommendation for future works, a different approach in dicing technology, namely laser grooving was proposed to eliminate ILD peeling and chipping. In conclusion, the optimized dicing recipe for 55nm node low-k wafer suggested by the DOE model are: (1) a thinner PO-base dicing tape, (2) a dicing blade with higher diamond concentration and finer grit size, (3) blade preparation / conditioning done with SiC board and (4) processing at lower spindle rotation and deeper cut depth are much preferred. The overall dicing responses and cutting quality has improved and is better compared to current production recipe.

Laser grooving process development for low-k / ultra low-k devices

In the past, mechanical sawing of low-k devices always poise to be a big challenge to achieve good dicing quality. This is because of the weak mechanical properties of low-k dielectric material used. Moving forward, this challenge will be even greater with the introduction of ultra low-k dielectric material in 45nm and 32nm wafer node size. An alternative dicing process such as laser grooving is gaining popularity in resolving the low-k saw problems. This paper discusses the development works of laser grooving and the following saw process of CMOS 90nm and 45nm devices, both in flip chip and wire bond packages. The discussion also includes wafer surface contamination prevention, laser process parameters selection, Heat Affected Zone (HAZ) analysis and laser process defects. A series of package reliability stress was carried out to prove the robustness of the finalized process parameters and conditions.

Single & multi beam laser grooving process parameter development and die strength characterization for 40nm node low-K/ULK wafer

This paper describes the development work on single and multi beam laser grooving technology for 40nm node low-k/ULK semiconductor device. A Nd:YAG ultraviolet (UV) laser diode operating at a wavelength of 355 nm was used in this study. The effects of single and multi beam laser micromachining parameters, i.e. laser power, laser frequency, feed speed, and defocus amount were investigated. The laser processed die samples were thoroughly inspected and characterized. This includes the die edge and die sidewall grooving quality, the grooving shape/profile and the laser grooving depth analysis. Die strength is important and critical. Die damage from thermal and ablation caused by the laser around the die peripheral weakens the mechanical strength within the die, causing a reduction in die strength. The strength of a laser grooved die was improved by optimizing the laser process parameter. High power optical microscopy, Scanning Electron Microscopy (SEM), and focused ion beam (FIB) were the inspection tools/methods used in this study. Package reliability and stressing were carried out to confirm the robustness of the multi beam laser grooving process parameter and condition in a mass production environment. The dicing defects caused by the laser were validated by failure analysis. The advantages and limitations of conventional single beam compared to multi beam laser grooving process were also discussed. It was concluded that, multi beam laser grooving is possibly one of the best solutions to consider for dicing quality and throughput improvements for low-k/ULK wafer dicing. The multi beam laser process is a feasible, efficient, and cost effective process compared to the conventional single beam laser ablation process.

Overcoming dicing challenges for low-K copper wafers using nickel-palladium-gold bond pads for automotive application

New automotive mission profiles include more than 3500 total hours at 150ºC. To satisfy new automotive requirements, plastic packages must meet AEC Grade 0 or higher. One key limitation of the conventional plastic package is the use of gold bond wire on aluminum bond pad. Au-Al intermetallic degradation due to intermetallic transformation in high temperature storage condition remains the main reliability concern. Pad re-metallization using nickel/palladium, nickel/gold or nickel/palladium/gold over aluminum bond pad or copper bond pad offers a noble and reliable metal interconnect. This study focused on the development of dicing process for low-K-copper wafers having aluminum pad re-metallized with electroless nickel / electroless palladium / immersion gold Over Pad Metallization (OPM). Development wafers were pizza mask wafers on which multiple die designs and scribe grid production control (SGPC) modules were designed. SGPC modules are designed with aluminum probe pads that are used to monitor wafer-level process control. All aluminum features on the wafer were plated with nickel/palladium/gold OPM. With nickel about four times as hard as aluminum, OPM plated SGPCs were much more difficult to dice than conventional SGPCs with aluminum pads. Cracking on silicon sidewall with crack propagating towards the die was found to cause back-end-of-line (BEOL) delamination and device failure. Surface roughness and hardness measurements were taken on OPM variations. Extensive mechanical dicing studies were conducted to modulate the failures and resolve the dicing challenge. Laser grooving followed by mechanical dicing of OPM wafers was also performed. Packages underwent extensive reliability stress conditions. The associated process improvements described in this paper supported a successful integration of a 55nm die technology in Low Profile Quad Flat Package with Exposed Pad (LQFP-EP) meeting and exceeding AEC grade 0 requirements.

Developments of blade dressing technique using SiC board for C90 low-k wafer sawing

Blade preparation or conditioning is one of the critical factors (aside from dicing blades, process parameters, and dicing tapes) one needs to consider, in order to establish optimum sawing parameters for good dicing quality. Blade dressing is important, to dispose off the excess bonding material and to expose the diamond particles for cutting. The conventional medium use to condition/season the dicing blade is silicon wafers. However, the total completion time to prepare a blade for wafer cutting usually takes a few hours. The new method proposed in this project is the use of a dressing board, which is of a silicon carbide-based (SiC) material. The positive impacts of using SiC board for blade dressing are significant improvements in saw machine capacity time, increasing production throughputs, and cost reduction on the usages of dressing materials such as Si mirror wafer, and dicing tapes. The time needed to prepare a blade for wafer sawing become shorter with the new board dressing method, which takes less than an hour to complete. The savings observed are about 98% of total time needed from the current dressing method. This paper presents all the development works done from (1) feasibility study stage on blade dressing board selection, dressing parameters optimization and establishment. Also, (2) pre-evaluations and confirmation run activities were performed on low/small samples of low-k wafer dicing using the new board dressing method until (3) final stages for actual new dressing process which will cover product qualification, validation and (4) implementation phases for high volume production of low-k wafer sawing. The topside saw ILD peeling size, topside saw chipping size, and backside chipping size are the critical dicing responses collected for statistical data analysis and interpretation. Optical visual inspection was conducted on post-processed low-k test wafers and several scribe structures (which comprised of different levels of metal density), for a thorough quantification and categorization on the peeling mode. Worst case peeling measurements and characterizations were conducted by using optical microscope, scanning electron microscopy (SEM) and focused ion beam (FIB). Electrical test and device reliability assessments were conducted to reflect and confirm the quality of the die samples which were diced using blade dressed with SiC board compared to control/traditional blade dressing method. The optimum dicing parameters dressed with the SiC board, was finally established and implemented in high volume manufacturing for low-k products. Last but not least, a proposed fan-out activity to qualify and implement the new board dressing method on current legacy/non low-k products was also discussed, as part of the recommendation for future works.

Packaging challenges in low-k silicon with thermally enhanced ball grid array (TE-PBGA)

All market segments continue to put cost pressure on semiconductor and packaging suppliers in order to stay competitive. Taking advantage of continuing silicon innovation in fabrication process, silicon area reduction and more device functionalities increase potential die count per wafer and lower the die cost. Staying in wire bond packaging instead of migrating to flip chip packaging further provides a cost competitive advantage. Wire bond packaging for silicon devices has been the backbone of the semiconductor industry to serve communications, automotive and networking customers for many years. Innovative interconnect routing and IC design and fine pitch wire bonding capability enable silicon to have 900 bonding pads in an area of 60mm2. High wire count and wire density is unprecedented in thermally enhanced plastic ball grid array (TE-PBGA) packages with an internal heat spreader, which is commonly denoted as TE-PBGA-II. With further shrink of the silicon dimension, low-k inter-layer dielectric (ILD) material has been widely used to replace the traditional SiO2 ILD in order to reduce the interconnect delay. Low-k dielectric by definition has a dielectric value of less than 3. The introduction of low-k ILD material into silicon imposes new challenges for high wire density packaging. In particular, the inherently weak adhesion in the low-k interconnect makes the silicon more susceptible to a failure mode called ILD crack or delamination that causes electrical failure during temperature cycling test. This paper will discuss challenges and resolution during the packaging development for low-k products with high wire density in large 31×31 and 35×35mm TE-PBGA-II packages. Challenges range from wafer dicing through difficult test structures in the scribe streets, die attach fillet height control, wire bonding on low-k bond pads, and molding low-k silicon in a large PBGA package with an internal heat spreader. Alternative methods including Finite Element Modeling and extended package reliability testing were used to demonstrate the robustness of the low-k packaging solution.

Multi beam laser grooving process parameter development and die strength characterization for 40nm node low-K/ULK wafer

This paper describes the development work of enabling a multi beam laser grooving technology for 40nm node low-k/ULK semiconductor device. A Nd:YAG ultraviolet (UV) laser diode operating at a wavelength of 355 nm was used in the study. The effects of multi beam laser micromachining parameters, i.e. laser power, laser frequency, feed speed, and defocus amount were investigated. The laser processed die samples were thoroughly inspected and characterized, which included the die edge and die sidewall grooving quality, the grooving shape/profile and the laser grooving depth examination. Die strength is important and critical. Die damage from thermal and ablation caused by the laser around the die peripheral weakens the mechanical strength within the die, causing a reduction in die strength. The strength of a laser grooved die was improved by optimizing the laser process parameter. High power optical microscopy, scanning electron microscopy (SEM), and focused ion beam (FIB) are the inspection tools/methods used in this study. Package reliability and stressing were carried out to confirm the robustness of the multi beam laser grooving process parameter and condition in a mass production environment. The dicing defects caused by the laser were validated by using failure analysis. The advantages and limitations of conventional single beam compared to multi beam laser grooving process were also discussed. It is shown that, multi beam laser grooving is possibly one of the best solutions to choose for dicing quality and throughput improvements for low-k/ULK wafer dicing. The multi beam laser process is a feasible, efficient, and cost effective process compared to the conventional single beam laser ablation process.

The characteristics and factors of a wafer dicing blade and its optimized interactions required for singulating high metal stack lowk wafers

Dicing a thick, 6 metal layer low-k Cu metallization wafer (from 90nm node wafer technology) is very challenging compared to the 4 metal layer stacked wafer. Poor topside cutting responses with excessive saw chip-outs were observed with the 6 metal layer. To resolve the saw chipping quality issue, a series of dicing assessments were performed, which includes: (1) saw machine baseline calibration and verification, (2) analysis study on the blades elements (diamond grit, diamond concentration, bond type) (3) new saw blade selection and evaluation, and (4) saw process parameter optimization and validation. This paper is focused on discussing the fundamentals of understanding each of the blade elements and its interaction on improving the topside chipping and peeling quality. Experimental studies were conducted by using various blade types and by varying the blade element composition. This includes variations in diamond grits sizes, diamond concentration (higher vs. lower diamond concentration), and bond type (softer vs. harder bond). A thorough process characterization was conducted to validate the cutting performance on the post-processed wafers. All results and data collected from the experimental studies were statistically analyzed and interpreted. In conclusion, a new saw blade with the appropriate selected blade attributes were introduced and qualified. With the optimized blade and saw parameters for the thick low-k Cu metallization wafers, topside chipping and peeling quality was significantly improved.