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Dive into the research topics where Varughese Mathew is active.

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Featured researches published by Varughese Mathew.


electronic components and technology conference | 2008

Electromigration of Cu-Sn-Cu micropads in 3D interconnect

Zhihong Huang; Ritwik Chatterjee; Patrick Justison; Richard Hernandez; Scott K. Pozder; Ankur Jain; Eddie Acosta; Donald A. Gajewski; Varughese Mathew; Robert E. Jones

There is significant interest in 3D interconnect technology due to its capability to provide fast, efficient inter-die interconnects at a minimum package footprint. Intermetallic Cu-Sn bonding has been widely investigated for 3D interconnects. However, the electromigration (EM) intrinsic reliability of the 3D Cu-Sn die-to-die microconnects has not been reported. In this paper the EM performance of 3D Cu-Sn microconnects formed by thermo-compression bonding is investigated and the failure mechanisms are discussed. The 3D stacked dice were assembled in wire bond ceramic packages and EM tests were conducted in both air and nitrogen ambient at various temperatures. Microconnect chain and Kelvin structures failure lifetime and the mean time to failure (MTTF) were measured. The failure analysis has been conducted and the possible failure mechanism has been proposed.


electronics packaging technology conference | 2010

High temperature automotive application: A study on fine pitch Au and Cu WB integrity vs. Ni thickness of Ni/Pd/Au bond pad on C90 low k wafer technology

Eu Poh Leng; Poh Zi Song; Au Yin Kheng; C.C. Yong; Tran Tu. Anh; John Arthur; Harold Downey; Varughese Mathew; Chee Yit Yin

For high temperature automotive application, IC products are required to pass stringent high temperature storage stress test (e.g. 5000hrs at 150 deg C), hence requires reliable wire bonds. Such requirement is especially challenging with fine pitch Au & Cu wire bond (e.g. bond pad pitch < 70um and bonded ball diameter < 58um), more-so on low k wafer technology with bond-over-active requirement.


electronic components and technology conference | 2011

Copper wire bonding on low-k/copper wafers with Bond Over Active (BOA) structures for automotive customers

Tu Anh Tran; Chu-Chung Lee; Varughese Mathew; Leo M. Higgins

The gold price has continuously climbing since 2000 and is currently recorded at historical high at above USD1350 per ounce in October 2010 as compared to USD1000 per ounce one year ago. Gold wire bonding has been the primary wire interconnecting method used in the semiconductor packaging industry for more than 50 years. Gold wire historically represented about 20-25% of the package cost. With the ever increasing gold price, this ratio now can be as high as 30-35% of the package cost and does not look like there is a relief in sight. Replacing gold wire with copper wire has become a necessity in order to maintain low assembly cost for wire bonded parts. Copper wire has many benefits including low cost, high electrical and thermal conductivities and excellent reliability with aluminum pad metallization. Heavy gauge copper wire has been used in consumer products and semiconductor discrete products for a long time. Many commercial product sectors began thin gauge copper wire in production since 2008. Automotive customers are also forced to look for cheaper interconnecting alternative, such as copper wire as an example. One of the issues in qualifying copper wire for automotive customers with stringent reliability requirements is that no industrial standard has been agreed or published to define copper wire qualification requirements. Presently most companies still apply gold wire reliability requirement to qualify copper wire packages. Many of them extend the gold wire package reliability stress duration for copper wire as a safety factor during the qualification. Our study is aimed for the assembly solution to apply copper wires on low-k-copper wafers with aggressive Freescale Bond Over Active (BOA) rules to meet automotive qualification requirements of Automotive Electronics Council (AEC) grade 1 and grade 0. Two types of bonding surfaces were used in this study, namely the conventional aluminum bond pad and aluminum bond pad remetallized with Nickel / Palladium / Gold Over Pad Metallurgy (OPM). Since Cu-Al and Cu-Au systems are completely different from Au-Al system, the difficulty in applying the same Au wire standards to copper wire parts will be discussed. A new approach to defining the pass/ fail criteria for copper wire parts will be proposed in this study. Units assembled with fine gauge copper wire were submitted through extensive stress conditions in order to demonstrate the excellent package reliability performance.


international electronics manufacturing technology symposium | 2010

A study on fine pitch Au and Cu WB integrity vs. Ni thickness of Ni/Pd/Au bond pad on C90 low k wafer technology for high temperature automotive

Eu Poh Leng; Poh Zi Song; Au Yin Kheng; C.C. Yong; Anh Tran Tu; John Arthur; Harold Downey; Varughese Mathew; Chee Yit Yin

For high temperature automotive application, IC products are required to pass stringent high temperature storage stress test (e.g. 5000hrs at 150 deg C), hence requires reliable wire bonds. Such requirement is especially challenging with fine pitch Au & Cu wire bond (e.g. bond pad pitch > 70um and bonded ball diameter < 58um), more-so on low k wafer technology with bond-over-active requirement.


electronic components and technology conference | 2016

Copper Ball Voids for Pd-Cu Wires: Affecting Factors and Methods of Controlling

Chu-Chung Lee; Varughese Mathew; Tu-Anh Tran; Rusli Ibrahim; Poh-Leng Eu

Bare copper wire has presented several challenges to both first and second bond wire bonding processes, such as Cu-Al intermetallic compound (IMC) corrosion induced by the mobile chlorine in the epoxy resin of the mold compound, and the narrow second bond process window. Palladium (Pd) coated copper wire has been developed to overcome these two challenges. However, the use of Pd-Cu wire is not a panacea to all Cu wire bond problems. One unique anomaly for Pd-Cu wire is the Cu ball void [1] which is observed only with Pd-Cu and not bare Cu ball bonds during HTSL (high temperature storage life) tests. The mechanism of forming Cu ball voids was proven to be the galvanized corrosion mechanism with Pd-Cu coupling. Significant factors affecting the formation rate of Cu ball voids are baking temperature, EFO current settings, bonding parameters and mold compound additives. Both anodic and cathodic chemical reactions have been proposed for Cu voids. A doped Cu wire has been proposed by many wire suppliers to overcome Cu ball voids and its pro and con will be summarized as compare to PdCu wires.


electronics packaging technology conference | 2012

Overcoming dicing challenges for low-K copper wafers using nickel-palladium-gold bond pads for automotive application

Tu Anh Tran; Varughese Mathew; Wen Shi Koh; K. Y. Yow; Yin Kheng Au

New automotive mission profiles include more than 3500 total hours at 150ºC. To satisfy new automotive requirements, plastic packages must meet AEC Grade 0 or higher. One key limitation of the conventional plastic package is the use of gold bond wire on aluminum bond pad. Au-Al intermetallic degradation due to intermetallic transformation in high temperature storage condition remains the main reliability concern. Pad re-metallization using nickel/palladium, nickel/gold or nickel/palladium/gold over aluminum bond pad or copper bond pad offers a noble and reliable metal interconnect. This study focused on the development of dicing process for low-K-copper wafers having aluminum pad re-metallized with electroless nickel / electroless palladium / immersion gold Over Pad Metallization (OPM). Development wafers were pizza mask wafers on which multiple die designs and scribe grid production control (SGPC) modules were designed. SGPC modules are designed with aluminum probe pads that are used to monitor wafer-level process control. All aluminum features on the wafer were plated with nickel/palladium/gold OPM. With nickel about four times as hard as aluminum, OPM plated SGPCs were much more difficult to dice than conventional SGPCs with aluminum pads. Cracking on silicon sidewall with crack propagating towards the die was found to cause back-end-of-line (BEOL) delamination and device failure. Surface roughness and hardness measurements were taken on OPM variations. Extensive mechanical dicing studies were conducted to modulate the failures and resolve the dicing challenge. Laser grooving followed by mechanical dicing of OPM wafers was also performed. Packages underwent extensive reliability stress conditions. The associated process improvements described in this paper supported a successful integration of a 55nm die technology in Low Profile Quad Flat Package with Exposed Pad (LQFP-EP) meeting and exceeding AEC grade 0 requirements.


electronic components and technology conference | 2000

Characterization of low alpha emissivity system on electroplated solder bumps

Addi Mistry; Sung Lee; Cynthia Enman; Barry Carroll; Douglas G. Mitchell; Varughese Mathew; Don Weeks; Michael Tucker

As attention to System Soft Error Rate (SSER) grows, better semiconductor design guidelines are being created. To protect sensitive transistor nodes from alpha particles emanating from trace amounts of natural occurring radioisotopes, improved shielding materials such as die coat barrier films are being used. In parallel, the demand for lower alpha emissivity materials is growing, such that semiconductor materials suppliers and packaging groups must certify their materials as being of a certain alpha emissive content. To this end, this alpha detection system continues to gain prominence, with detection capabilities down to 0.001 alpha count/cm/sup 2//hour and sample measurement sizes to 1000 square centimeters. This study outlines a method of characterization and determines capability of the continuous gas flow proportional counter.


Archive | 2008

CONDUCTIVE BRIDGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MAKING THE SAME

Varughese Mathew; Sam S. Garcia; Tushar P. Merchant


Archive | 2002

Method of forming a component overlying a semiconductor substrate

Lakshmi N. Ramanathan; Douglas G. Mitchell; Varughese Mathew


Archive | 2003

Semiconductor process and composition for forming a barrier material overlying copper

Varughese Mathew; Sam S. Garcia; Christopher M. Prindle

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Eddie Acosta

Freescale Semiconductor

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Tu Anh Tran

Freescale Semiconductor

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