Ka Lok Man

Composition challenges and approaches for cyber physical systems

A wide variety of programming abstractions have been developed for cyber-physical systems. These approaches provide support for the composition of cyber-physical systems from generic units of application functionality. This paper surveys the current state-of-the-art in composition mechanisms for cyber physical systems and reviews each approach in terms of its support for composition analysis, re-use and adaptation. We then review approaches for modeling and verifying cyber-physical application compositions and conclude by proposing promising research directions that will address these shortcomings.

A middleware platform to support river monitoring using wireless sensor networks

Flooding is a critical global problem, which is growing more severe due to the effects of climate change. This problem is particularly acute in the state of São Paulo, Brazil, where flooding during the rainy season incurs significant financial and human costs. Another critical problem associated with flooding is the high level of pollution present in urban rivers. Efforts to address these problems focus upon three key research areas: river monitoring, modelling of river conditions and incident response. This paper introduces a rich next-generation middleware platform designed to support wireless sensor network based environmental monitoring along with a supporting hardware platform. This system has been deployed and evaluated in a real-world river monitoring scenario in the city of São Carlos, Brazil.

HotSpot : Visualizing dynamic power consumption in RTL designs

We propose `HotSpot, a tool for the visualization of dynamic power consumption in RTL designs. Using an RTL simulation, the amount of switching activity at major circuit nodes is determined. This information is annotated onto a custom graph of the circuit in the form of `temperature colour coding. HotSpot highlights areas in which switching activity (and thereby dynamic power consumption) may be reduced. We survey some existing techniques for dynamic power minimization and discuss how HotSpot may identify opportunities for the application of such techniques at RTL. We believe this could lead to reduced power consumption, faster design turnaround and better design practices in future.

A low-power pairing-based cryptographic accelerator for embedded security applications

We report on the implementation of an IP core for Pairing-based cryptography. The core performs an elliptic curve cryptographic operation called the Tate Pairing over the field GF(2251). In this paper, we describe the implementation of the design in TSMC 65nm GP CMOS standard cells and the optimisations made for low-power operation. The resulting core computes the pairing in 1.5ms and consumes less than 4mW.

Performance and Functional Analysis of TLM Models in the SHE Methodology

Software/hardware engineering (SHE) is a model-driven system-level design methodology for hardware/software systems and embedded systems. It assists a designer in both the development of models for analysis purposes and the actual realisation of the system; and the toolset of SHE is the result of software engineering research with a very strong foundation in formal theories/methods. In the recent years, the transaction level modelling (TLM) paradigm has been widely propagated for complex system-on-a-chip (SoC) and embedded system designs; and it is being used in industry to solve a variety of practical problems during the design, development and deployment of such designs. This paper presents the application of the SHE methodology to combine performance and functional analysis of TLM models. We illustrate the practical interest of our approach with an example: a CPU and memory system.

SC2SCFL: Automated SystemC to

SystemCFL is the formalisation of a reasonable subset of SystemC based on classical process algebras. During the last few years, SystemCFL has been successfully used to give formal specifications of SystemC designs. For formal analysis purposes, so far, users have been required to transform manually their SystemC codes into corresponding SystemCFL specifications. To verify some desired properties of SystemCFL specifications using existing formal verification tools (e.g. NuSMV and SPIN), similarly, manual translations have been needed for turning SystemCFL specifications into corresponding terms of the input language (e.g. SMV and PROMELA) of the selected formal verification tool. Since manual transformation and translations between SystemC codes, SystemCFL specifications, and various formalisms are quite laborious and therefore error-prone, these translations have to be made as much automatic as possible. The first step of the research in these directions is to automate the transformation from SystemC codes to SystemCFL specifications. In this paper, we present SC2SCFL (an automatic translation tool), which converts SystemC codes into corresponding SystemCFL specifications.

SystemC^{\mathbb{FL}}

A software component is defined as a unit of composition with contractually specified interfaces and explicit dependencies that may be independently deployed. Components form generic, re-usable software building blocks, which can be composed into applications and deployed by third parties. A good component model therefore must seek to minimize implicit dependencies in order to maximize re-use and composability. The benefits of component models have led to their widespread application in the area of networked embedded systems and particularly Wireless Sensor Networks. This paper first classifies and analyses the types of dependency that a component may be subject to. Next, we assess the success of contemporary component models in eliminating implicit dependencies and promoting re-usability. We then describe our efforts to reduce implicit distributed dependencies in the design of LooCI: the Loosely-coupled Component Infrastructure. We conclude with a call-to-arms for the component-based software engineering community that suggests avenues for future work.

Translation

Structural representation and technology mapping of a Boolean function is an important issue in the design of digital circuits. Various data structures such as Binary Decision Diagrams (BDDs), And Inverter Graphs (AIGs) and Nand Nor Inverter Graphs (NNIGs) have been widely used for structural representation, logic synthesis and technology mapping of digital circuits. The tool ABC has been developed for the logic synthesis and manipulation of AIGs. This paper presents a tool which builds and manipulates NNIGs as a sub-package in ABC. To the best of our understanding, it is the first tool developed for the manipulation of NNIGs. Experimental results illustrate the applicability and efficiency of the tool. The paper also presents a new data structure Probabilistic Timed Nand-Nor-Inverter Graph (PTNNIG) that can be used for accurate power estimation and timing analysis of digital circuits. Such data structures are incorporated with probability and timing as parameters and will lead to a better and combined power and timing analysis.

Eliminating implicit dependencies in component models

As part of our ongoing research, we present BSAA - Bus Switching Activity Analyser - a CAD tool which reads switching activity from RTL simulation, extracting a list of the circuits buses and associated switching activity metrics. The list is filtered and sorted according to user-specified criteria, producing reports and a set of graphical switching activity profiles of the circuits most active buses. The tool identifies common profiles corresponding to typical address- and data bus traffic. As part of a CAD flow, BSAA enables rapid switching activity analysis and encoding design for switching minimisation on heavily-loaded cross-chip buses and IO pins.

Data structure manipulation for NNIG and PTNNIG: Towards a unified power and timing analysis

Support Vector Machine (SVM) classifiers are binary classifiers in nature, which have to be coupled/assembled to solve multi-class problems. One-Versus-Rest (1-v-r) is a fast and accurate method for SVM multiclass classification. This paper investigates the effect of output grouping on multiclass classification with SVM and offers an even faster version of 1-v-r based on our output grouping algorithm.