Maurice Keller

Hardware architectures for the Tate pairing over GF(2m)

In this paper two different approaches to the design of a reconfigurable Tate pairing hardware accelerator are presented. The first uses macro components based on a large, fixed number of underlying Galois Field arithmetic units in parallel to minimise the computation time. The second is an area efficient approach based on a small, variable number of underlying components. Both architectures are prototyped on an FPGA. Timing results for each architecture with various different design parameters are presented.

FPGA implementation of a GF(2/sup 2M/) multiplier for use in pairing based cryptosystems

In this paper an architecture for GF(2/sup 4m/) multiplication is outlined. It is illustrated how this operation is critical to efficient hardware implementation of the Tale pairing, which itself is the underlying calculation in many new pairing based cryptosystems. Tate pairing calculation times using an FPGA hardware accelerator are estimated based on results from the multiplier architecture.

Elliptic Curve Cryptography on FPGA for Low-Power Applications

Elliptic curve cryptography has generated a lot of research interest due to its ability to provide greater security per bit compared to public key systems such as RSA. The designer of an elliptic curve hardware accelerator is faced with many choices at design time, each of which can impact the performance of the accelerator in different ways. There are many examples in the literature of how these design choices can effect the area and/or speed of an elliptic curve hardware accelerator. The effect of design choices on power and energy consumption in elliptic curve hardware has been less well studied. This article studies the effect of design choices on the power and energy consumption of an FPGA-based reconfigurable elliptic curve hardware accelerator. A reconfigurable processor has been used for different system parameters and the power and energy consumption measured. The power and energy results are presented and compared.

Low power elliptic curve cryptography

The designer of an elliptic curve processor is faced with many design choices that include the algorithm and coordinate system to be used. The power consumption of elliptic curve processors is becoming increasingly important as such processors find new uses in power constrained environments. This paper studies the effect that algorithm and coordinate choices have on the power consumption and energy per point multiplication of an FPGA based, reconfigurable elliptic curve processor.

A low-power pairing-based cryptographic accelerator for embedded security applications

We report on the implementation of an IP core for Pairing-based cryptography. The core performs an elliptic curve cryptographic operation called the Tate Pairing over the field GF(2251). In this paper, we describe the implementation of the design in TSMC 65nm GP CMOS standard cells and the optimisations made for low-power operation. The resulting core computes the pairing in 1.5ms and consumes less than 4mW.

Network-on-Chip interconnect for pairing-based cryptographic IP cores

On-chip data traffic in cryptographic circuits often consists of very long words or large groups of smaller words exchanged between processing elements. The resulting wide cross-chip buses exhibit power, congestion and scalability problems. In this paper, two case study cryptographic IP cores with demanding interconnect requirements are implemented on 65nm CMOS. Lightweight, custom bus-replacement Networks-on-Chip (NoCs) have been developed for both cores. Results show that eliminating the 251-bit-wide cross-chip cryptographic buses dramatically improves the quality of physical implementation. The results have applicability to wire-constrained designs in other domains.

A GF(24m) Inverter and its Application in a Reconfigurable Tate Pairing Processor

This paper details an architecture for performing inversion in the field GF(24m), which is the field used in computing the Tate pairing on characteristic 2 supersingular elliptic curves. The inverter architecture is then used to improve the performance of a reconfigurable Tate pairing hardware accelerator. Implementation results for the improved processor on an FPGA are presented and compared to those of the basic processor without the inverter

Low Energy ASIC Elliptic Curve Processor

Elliptic curve cryptography is highly suited for implementation in resource constrained environments, however, dedicated hardware accelerators are necessary to provide the low power/energy security required in small, battery powered devices. This paper presents a low energy ASIC implementation of a characteristic 2 elliptic curve processor which consumes minimal energy per point multiplication, thereby prolonging battery life in constrained devices. Energy consumption is minimised by using low power design techniques in conjunction with an efficient, low area architecture in order to reduce the power consumption while maintaining a low number of clock cycles per operation. The energy/power/area trade-off is explored. In 0.13 μm CMOS technology the architecture consumes a minimum of 1.32 μJ at 500 kHz using a digit size of 15 and 24.6 kgates. The best area/energy trade off was 1.43 μJ at 500 kHz using a digit size of 11 and 22.3 kgates.

Energy Efficient Elliptic Curve Processor

Elliptic curve cryptography is highly suited for implementation in resource constrained environments, however, dedicated hardware accelerators are necessary to provide the low power/energy security required in small, battery powered devices. This paper presents a low energy ASIC implementation of an elliptic curve processor which consumes minimal energy per point multiplication, thereby prolonging battery life in constrained devices. The energy/power/area trade-off is explored. In 0.13 μm CMOS technology the architecture consumes a minimum of 1.32μJ at 500 kHz using a digit size of 15 and 24.6 kgates.