Kai-Yuan Jheng

Traffic- and Thermal-Aware Run-Time Thermal Management Scheme for 3D NoC Systems

Three-dimensional network-on-chip (3D NoC), the combination of NoC and die-stacking 3D IC technology, is motivated to achieve lower latency, lower power consumption, and higher network bandwidth. However, the length of heat conduction path and power density per unit area increase as more dies stack vertically. Routers of NoC have comparable thermal impact as processors and contributes significant to overall chip temperature. High temperature increases the vulnerability of the system in performance, power, reliability, and cost. To ensure both thermal safety and less performance impact from temperature regulation, we propose a traffic- and thermal-aware run-time thermal management (RTM) scheme. The scheme is composed of a proactive downward routing and a reactive vertical throttling. Based on a validated traffic-thermal mutual-coupling co-simulator, our experiments show the proposed scheme is effective. The proposed RTM can be combined with thermal-aware mapping techniques to have potential for higher run-time thermal safety.

Traffic-thermal mutual-coupling co-simulation platform for three-dimensional Network-on-Chip

Thermal issue is one of the major challenges in the research field of three-dimensional (3D) IC. Network-on-Chip (NoC) has been viewed as a practical communication infrastructure for 3D IC. To facilitate such research, an accurate and non-proprietary environment for simulating the NoC traffic and temperature is necessary. In this paper, we present a traffic-thermal mutual-coupling co-simulation platform for 3D NoC. The translation error is eliminated, and therefore our co-simulation has no accuracy loss on mutual coupling. Our simulation results, validated with a commercial tool, show the temperature error of our platform is between −1 and 4 K. The simulation results also show the thermal profile of 3D NoC, in which the temperature is imbalance even under the balanced traffic. Hence, the proposed platform can be used for 3D thermal-aware design, 3D dynamic thermal management technology, and other related researches in the future.

Multilevel LINC System Design for Wireless Transmitters

Linear amplifier with nonlinear components (LINC) is a power linearization method which offers both high linearity and high power amplifier (PA) efficiency in wireless transmitters. While LINC increases the power efficiency of PAs, this linearization technique requires an extra power combiner which results in low power efficiency of whole system. To improve this drawback, we propose a multi-level LINC (ML-LINC) method to not only increase power combiner efficiency but also maintain high linearity of wireless transmitters. We also derive the optimal value of each scaling level to maximize the power combiner efficiency. Finally, we demonstrate a four-level scaling ML-LINC as a design example which enhances power combiner efficiency from 44.5% to 80.8% and maintains high linearity to fulfill WCDMA specifications.

Multilevel LINC System Designs for Power Efficiency Enhancement of Transmitters

To meet the linearity requirements of novel wireless communication standards using varying-envelope modulations, the class A power amplifier (PA) in the traditional transmitters must be highly backed off to work in the linear region where power efficiency drops rapidly. As for the PA linearization technique, linear amplifier with nonlinear components (LINC), achieves linear amplification without power backoff. However, the combiner power efficiency of the LINC system degrades significantly for signals with a high peak-to-average power ratio. In this paper, we propose a multilevel out-phasing (MOP) scheme to achieve high combiner efficiency by reducing the signal dynamics. Furthermore, based on the MOP, we design two architectures: envelope-adjusting MLINC (EA-MLINC) and gain-adjusting MLINC (GA-MLINC). Under the WCDMA system linearity requirements, the simulations show that 3-level EA-MLINC and 3-level GA-MLINC enhance the LINC system power-added efficiency from 16.5% to 33.4% and 23.6%, respectively.

Multilevel Linc System Design for Power Efficiency Enhancement

Linear amplifier with nonlinear components (LINC) is a power amplifier (PA) linearization technique which offers both high PA efficiency and high linearity of wireless transmitters. But at the output stage, LINC uses a power combiner which results in low system efficiency. To solve this problem, we propose a multilevel out-phasing (MOP) scheme and a corresponding architecture, multilevel LINC (MLINC), to increase power combiner efficiency of wireless transmitters. Under WCDMA system linearity requirements, we demonstrate the 3-level MLINC as a design example which enhances power combiner efficiency from 44.5% to 75.5%.

A design flow for multiplierless linear-phase FIR filters: from system specification to Verilog code

This work presents a design flow for the multiplierless linear-phase FIR filter synthesizer, which combines several research efforts. We propose a local search algorithm with variable filter order to reduce the number of adders further. In addition, several design techniques are adopted to reduce the hardware complexity of the system. By using this synthesizer, the system designers can design a filter efficiently and a chip can be successfully finished in a very short time.

ACO-based Cascaded Adaptive Routing for traffic balancing in NoC systems

Ant Colony Optimization (ACO) is a bio-inspired algorithm extensively applied in optimization problems. The performance of Network-on-Chip (NoC) is generally dominated by traffic distribution and routing. With more precise network information for path selection by using pheromone, ACO-based adaptive routing has higher potential to overcome the unbalance and unpredictable traffic load. On the other hand, the implementation cost of ACO is in general too high to store network information in pheromone memory, which is a routing table of all destination-channel pairs. We propose an ACO-based Cascaded Adaptive Routing (ACO-CAR) by combining two features: 1) table reforming by eliminating redundant information of far destinations from full routing table, and 2) adaptive searching of cascaded point for more precise network information. Our experimental results show that ACO-CAR has lower latency and higher saturation throughput, and can be implemented with 19.05% memory of full routing table.

Polar transmitter for wireless communication system

Polar modulation techniques offer the capability of multimode wireless system and the potential for the high efficiency power amplifier (PA). Any input baseband complex signal is decomposed into magnitude and phase signal, and goes through envelope modulator and phase modulator respectively. The modulated envelope and phase message signals are combined and amplified by switched-mode PA. In this paper, we will focus on the rectangular-to-polar converter, envelope modulator and phase modulator of polar transmitter for EDGE (2.5G) system. The analog part includes open-loop envelope modulator. The digital part includes rectangular-to-polar converter and digital phase modulator. We employ the coordinate rotation digital computer (CORDIC) and direct digital frequency synthesizer (DDFS) techniques in this part. A prototype chip has been designed and fabricated in UMC 0.18 /spl mu/m CMOS process with 1P6M technology.

Multiplierless multirate decimator/interpolator module generator

A module generator, which can automate the process of designing high-speed low-complexity multistage multirate decimator/interpolator, is presented. The generator exploit architectural symmetries in linear phase filters and multistage multirate interpolated FIR filter design methodology for low complexity. In addition, the polyphase representation is used to decompose the filter into subfilters. The resulting filters utilize canonic signed digit (CSD) multipliers, a transposed direct form structure, and carry-save addition for high speed. A filter design example with TSMC 0.25 /spl mu/m standard cell for 64-QAM baseband demodulator shows that the area is reduced by 39% for low-complexity applications. Moreover, for high-speed application, the chip can operate at 714MHz. Finally, a designed decimator which is used in the CDMA cellular shows that the area is reduced by 70% as compared with conventional approach.

High-convergence-speed low-computation-complexity SVD algorithm for MIMO-OFDM systems

Multiple-input multiple-output (MIMO) wireless communication systems with orthogonal frequency-division multiplexing (OFDM) achieve high spectral efficiency high channel capacity, and many MIMO-OFDM systems use the spatial multiplexing technique to improve the system performance. The MIMO-OFDM systems require the singular values and the corresponding singular vectors of the channel matrix by exploiting singular value decomposition (SVD). The information of the right singular-vector matrix can be fed back to the transmitter for linear precoding to improve the error performance when facing the channel matrix with rank deficiency problem. This work proposes a SVD algorithm with fast convergence speed, which is suitable for the MIMO channels with short coherent time. The proposed SVD algorithm has the following features: (1) low total computational complexity, (2) fast convergence speed, (3) the ability of reconfigurable to different numbers of transmitter and receiver antennas, and (4) insensitive to the dynamic range problem, which is suitable for hardware implementation.