Chung-Chun Chen

Design and Analysis for a 60-GHz Low-Noise Amplifier With RF ESD Protection

An RF electrostatic discharge (ESD) protection for millimeter-wave (MMW) regime applied to a 60-GHz low-noise amplifier (LNA) in mixed-signal and RF purpose 0.13-mum CMOS technology is demonstrated in this paper. The measured results show that this chip achieves a small signal gain of 20.4 dB and a noise figure (NF) of 8.7 dB at 60 GHz with 65-mW dc power consumption. Without ESD protection, the LNA exhibits a gain of 20.2 dB and an NF of 7.2 dB at 60 GHz. This ESD protection using an impedance isolation method to minimize the RF performance degradation sustains 6.5-kV voltage level of the human body model on the diode and 1.5 kV on the core circuit, which is much higher than that without ESD protection (< 350 V). To our knowledge, this is the first CMOS LNA with RF ESD protection in the MMW regime and has the highest operation frequency reported to date.

Design and Analysis of CMOS Frequency Dividers With Wide Input Locking Ranges

A millimeter-wave (MMW) frequency synthesizer needs a low-power frequency divider (FD) with a wide input locking range to ensure reliability and lower power operation. In this paper, the design and analysis of low-power wide locking range MMW FDs are presented. Proposed are two divide-by-2 (D2) and divide-by-4 (D4) FDs that achieve the widest locking range reported to date by using a dual-mixing technique. Both FDs are fabricated in 90-nm CMOS and are demonstrated to achieve very wide input locking ranges without any tuning mechanism. At an input power of 0 dBm, the D2 FD has a locking range of 51-74 GHz, and that of the D4 FD is 82.5-89 GHz. The power consumption is only 3 mW for both the D2 FD and the D4 FD, from a 0.5 V supply. The proposed D2 and D4 FDs may facilitate incorporation into a product of a MMW phase-locked loop that is smaller, consumes less power, and is more reliable than the conventional approach.

Ring-Based Triple-Push VCOs With Wide Continuous Tuning Ranges

This paper proposes a new ring-based triple-push voltage-controlled oscillator (VCO) architecture to achieve a wide tuning range and high operating frequencies. Two ring-based triple-push VCOs, one with a continuous frequency tuning range of 0.2-34 GHz, fabricated in 0.13- mum CMOS, and the other with a range of 0.1-65.8 GHz, fabricated in 90-nm CMOS, are presented in this paper. These two VCOs demonstrate that the proposed VCO architecture can achieve a very wide continuous tuning range, up to millimeter-wave frequencies, without any device-switching operations. In addition to the wide tuning range, the chip area of the proposed VCO is very small, allowing integration into a phase-locked loop. The power consumptions of the 0.2-34- and 0.1-65.8-GHz VCOs are 2-70 mW from a 2-V supply voltage, and 1.2-26.4 mW from a 1.2-V supply voltage, respectively. The fundamental and second harmonic rejections are better than 15 dB for both VCOs.

Anorectal function and endopelvic dissection in patients with repaired imperforate anus

Abstract Fifty-eight patients with anorectal malformations were closely followed up for postoperative anorectal function. Constipation was noted shortly after anorectoplasty in 10 of 28 low anomalies (35.7%) treated with limited sagittal anorectoplasty (LSARP), in 18 of 25 high or intermediate anomalies (72.0%) treated with posterior sagittal anorectoplasty (PSARP), but in none of 5 high or intermediate anomalies treated with Rehbeins mucosa-stripping endorectal pull-through and anterior sagittal perineal anorectoplasty (R-ASAP). The constipation resolved mostly within 1–2 years after repair under conservative management, but persisted beyond 2 years after repair in 3/25 children with LSARP and 10/25 with PSARP. Anal soiling was noted in 1/23 (4.3%) LSARP and 6/22 (27.3%) PSARP patients, but normal anorectal function was attained in 20/23 LSARP (86.9%) and 11/22 PSARP patients (50.0%) by the time of toilet training. Manometric studies disclosed that the resting rectal pressure (RRP) was lower and the anorectal pressure gradient (ARPG) higher in the constipated than the non-constipated children, while the RRP was higher and the ARPG lower in the soiled than the non-soiled patients. The ARPG after R-ASPA was close to that of non-constipated and in between that of the constipated and soiled patients. The rectoanal sphincter inhibitory reflex was not related to defecation status or surgical procedures, but showed a tendency toward positive conversion with time or after exclusion of ectatic terminal bowel in the severely constipated. It is concluded that anorectal function in patients with repaired imperforate anus seems to be more affected by the extent of endopelvic dissection than by preservation of the terminal bowel or sphincter muscles.

Low Insertion-Loss Single-Pole–Double-Throw Reduced-Size Quarter-Wavelength HEMT Bandpass Filter Integrated Switches

This paper proposes a circuit topology which reduces the chip size of single-pole-double-throw (SPDT) quarter-wavelength bandpass filter-integrated switches (FIS). A 40-GHz mHEMT MMIC SPDT switch has been implemented and demonstrates a measured insertion loss lower than 1 dB and an isolation better than 30 dB. Another 50-GHz pHEMT MMIC SPDT achieves 1.5 dB insertion loss and 22 dB isolation. The low insertion loss and high isolation shows that the circuit performance is improved along with the reduction of the size. The systematic design approach of the reduced-size FIS is described, together with the analysis of the insertion loss and isolation.

Polar transmitter for wireless communication system

Polar modulation techniques offer the capability of multimode wireless system and the potential for the high efficiency power amplifier (PA). Any input baseband complex signal is decomposed into magnitude and phase signal, and goes through envelope modulator and phase modulator respectively. The modulated envelope and phase message signals are combined and amplified by switched-mode PA. In this paper, we will focus on the rectangular-to-polar converter, envelope modulator and phase modulator of polar transmitter for EDGE (2.5G) system. The analog part includes open-loop envelope modulator. The digital part includes rectangular-to-polar converter and digital phase modulator. We employ the coordinate rotation digital computer (CORDIC) and direct digital frequency synthesizer (DDFS) techniques in this part. A prototype chip has been designed and fabricated in UMC 0.18 /spl mu/m CMOS process with 1P6M technology.

A 40-to-76 GHz Balanced Distributed Doubler in 0.13-μm CMOS Technology

A miniature 40- to 76-GHz monolithic balanced distributed frequency doubler is developed in a commercial 0.13-mum CMOS process. This balanced doubler consists of a reduced-size broadside-coupled Marchand balun and two distributed doublers, and suppresses fundamental signals better than 25 dB. The measured conversion losses are 8-11 dB for the output frequencies from 40 to 76-GHz under 6-dBm input drive, with a low dc power consumption of 12 mW. The chip size is 0.64 times 0.65 mm2. To the best of our knowledge, this doubler achieves the widest bandwidth among all the CMOS doublers reported to date.

3 mW V-band divide-by-2 and W-band divide-by-4 wide locking range frequency dividers in 90-nm CMOS

The proposed divide-by-2 (D2) and divide-by-4 (D4) frequency dividers (FDs) achieve the widest locking range reported to date by using a dual-mixing technique in 90-nm CMOS. At an input power of 0 dBm, the D2 FD demonstrates a locking range of 51–74 GHz, and the D4 FD one of 82.5–90 GHz, without any tuning mechanism. The power consumption is only 3 mW for both the D2 FD and the D4 FD, from a 0.5 V supply.

Dual-band CDR using a half-rate linear phase detector

This paper describes a dual-band clock and data recovery circuit using a new half-rate linear phase detector. With the proposed sampling scheme, the phase detector produces UP/DN signals with equal pulsewidth and thus eliminates the demand of current scaling in the charge pump. The test chip fabricated by CMOS 0.18 μm 1P6M process can operate at 2.7 and 1.62 Gbps which satisfies the DisplayPort standard. It can recover the NRZ data of a (27-1) PRBS with a bit error rate less than 10−12. The chip core occupies an area of 0.36 mm2. The power consumption is 50 mW at 2.7 Gbps with a 1.8 V supply voltage.

A 460MHz∼870MHz CMOS wideband low noise amplifier for DVB-T

This paper focuses on a wideband low noise amplifier (LNA) for DVB-T fabricated with the TSMC 0.18 mum CMOS process. The proposed wideband LNA, from 460 MHz to 870 MHz, achieves a wideband and flat gain property by using the resistive feedback technique. Compared with other wideband LNAs, the proposed circuit can achieve a flatter gain curve, a flatter IIP3 in band, and a small chip area. The overall power gain of the proposed LNA is 21.5 dB to 21.8 dB. It simply varies 0.3 dB in band. Sll is smaller than -12.7 dB, and S22 is smaller than -12 dB. Noise Figure (NF) is 3 dB~4.7 dB, and IIP3 is -5 dBm~-5.6 dBm in band.