Kailash C. Jain

Characteristics of trench j-MOS power transistors

The fabrication of trench j-MOS transistors in bulk silicon, so that they can be operated in either a three-terminal or a four-terminal mode, is presented. When the transistors are operated in accumulation mode, the specific on-resistance is 0.8 m Omega -cm/sup 2/. In the four-terminal mode a high transconductance, 290 S/cm/sup 2/, is achieved by manipulating the inversion layer charge. In the three-terminal mode, mixed pentode-triode drain characteristics are exhibited. Response times are comparable to those of a junction FET. These properties make the trench j-MOS transistor attractive for power switching.<<ETX>>

A thyri-magnetodiode

The magnetic field sensitivity of p-i-n diodes fabricated in silicon-on-sapphire (SOS) depends on the establishment of a bipolar conduction region. Because of low effective lifetimes of the SOS material, tau /sub eff/ approximately=10 ns, the bipolar regime occurs at high electric fields, the junction temperature rises, and magnetosensitivity is reduced. The reproducibility of Si-Al/sub 2/O/sub 3/ interfaces is also a problem. A novel two-terminal devices has been built in 5-10 Omega -cm n-type 1.0- mu m-thick

Whole-Field Residual Stress Measurements In Silicon Wafers During Integrated Circuit Fabrication

An optical method is proposed which generates the two-dimensional out-of-plane partial contours of silicon wafers and requires only a single numerical differentiation to compute the whole-field residual stress distribution. The optical arrangement for the method requires the use of either a linear or a crossed grating and two large lenses. At the recording stage, this arrangement results in an instantaneous reconstruction of the grating lines into the contours of partial slopes of the wafer. Visual inspection of these contours allows an immediate qualitative evaluation of the local stress variations. Contours with good contrast are obtained even for wafers with circuits printed on them. The partial curvatures are obtained by numerically differentiating the slope contour data. The wafer is modelled as a composite structure consisting of a thin film deposited on the silicon substrate. The two-dimensional residual stress distributions in the film and the substrate are obtained from the curvatures using a plate bending theory approach. The proposed method was used to follow the development of residual stresses in silicon wafers during integrated circuit fabrication using an n-MOS silicon gate process. It was found that the local oxidation step introduced maximum residual stresses whereas the metalization step had a small counter influence on the stresses. The local residual stress variations were enough to cause the conventional average measure to be in error by a factor of two even for wafers without stacking faults. This method can be a valuable tool for a fast and accurate quality control of incoming and outgoing wafers, and can provide useful guidelines for wafer fabrication process research.